公开(公告)号：US20240205363A1

公开(公告)日：2024-06-20

申请号：US18444524

申请日：2024-02-16

Applicant: Apple Inc.

Inventor： David R. POPE ,  Liran FISHEL ,  Assaf METUKI ,  Muge WANG

IPC: H04N5/76 ,  G06T1/60 ,  G06T7/246 ,  H04N1/21

CPC classification number: H04N5/76 ,  G06T1/60 ,  G06T7/251 ,  H04N1/2141 ,  G06T2207/20016

Abstract: Embodiments relate to extracting features from images, such as by identifying keypoints and generating keypoint descriptors of the keypoints. An apparatus includes a pyramid image generator circuit, a keypoint descriptor generator circuit, and a pyramid image buffer. The pyramid image generator circuit generates an image pyramid from an input image. The keypoint descriptor generator circuit processes the pyramid images for keypoint descriptor generation. The pyramid image buffer stores different portions of the pyramid images generated by the pyramid image generator circuit at different times and provides the stored portions of the pyramid images to the keypoint descriptor generator circuit for keypoint descriptor generation. When first portions of the pyramid images are no longer needed for the keypoint descriptor generation, the first portions are removed from the pyramid image buffer to provide space for second portions of the pyramid images that are needed for the keypoint descriptor generation.

公开(公告)号：US20250165748A1

公开(公告)日：2025-05-22

申请号：US19030926

申请日：2025-01-17

Applicant: APPLE INC.

Inventor： Liran FISHEL ,  Erik K. NORDEN

IPC: G06N3/04 ,  G06F9/50 ,  G06N3/08

Abstract: Embodiments relate to managing tasks that when executed by a neural processor circuit instantiates a neural network. The neural processor circuit includes neural engine circuits and a neural task manager circuit. The neural task manager circuit includes multiple task queues and a task arbiter circuit. Each task queue stores a reference to a task list of tasks for a machine learning operation. Each task queue may be associated with a priority parameter. Based on the priority of the task queues, the task arbiter circuit retrieves configuration data for a task from a memory external to the neural processor circuit, and provides the configuration data to components of the neural processor circuit including the neural engine circuits. The configuration data programs the neural processor circuit to execute the task. For example, the configuration data may include input data and kernel data processed by the neural engine circuits to execute the task.

公开(公告)号：US20250165747A1

公开(公告)日：2025-05-22

申请号：US19030867

申请日：2025-01-17

Applicant: APPLE INC.

Inventor： Erik Norden ,  Liran FISHEL ,  Sung Hee PARK ,  Jaewon SHIN ,  Christopher L. MILLS ,  Seungjin LEE ,  Fernando A. MUJICA

IPC: G06N3/04 ,  G06F1/3296 ,  G06N3/08

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

公开(公告)号：US20240143483A1

公开(公告)日：2024-05-02

申请号：US18406036

申请日：2024-01-05

Applicant: Apple Inc.

Inventor： Liran FISHEL ,  Danny GAL ,  Nir NISSAN

IPC: G06F11/36 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F11/3636 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30145 ,  G06F9/321 ,  G06F11/3656

Abstract: Embodiments of the present disclosure relate to debugging of an accelerator circuit using a packet limit breakpoint. A vector circuit reads a subset of instruction packets from an instruction memory and receives a portion of input data from a data memory corresponding to the subset of instruction packets. The vector circuit executes a set of vector operations in accordance with multiple instruction packets from the subset using data from the received portion of input data identified in the multiple instruction packets to generate output data. A program counter control circuit coupled to the instruction memory triggers a breakpoint in a program stored in the instruction memory causing the accelerator circuit to stop executing remaining instruction packets in the program following the multiple instruction packets responsive to a number of instruction packets executed in the program from a time instant of an event reaching a predetermined number.

公开(公告)号：US20250054274A1

公开(公告)日：2025-02-13

申请号：US18932195

申请日：2024-10-30

Applicant: Apple Inc.

Inventor： Assaf METUKI ,  Lukas POLOK ,  Danny GAL ,  Liran FISHEL

IPC: G06V10/75 ,  G06V10/74

Abstract: Embodiments of the present disclosure relate to selecting a subset of keypoint descriptors of two images for match operation based on their orientation angles indicated in headers of the keypoint descriptors. The keypoint descriptors in the two images are matched by first comparing their headers and then performing vector distance determination. During the header comparison operation, a header of a descriptor of a first image is compared only with headers of keypoint descriptors of a second image in a discrete orientation angle range corresponding to an orientation angle indicated by the header of the first image descriptor or keypoint descriptors of the second image in adjacent discrete orientation angle ranges. After the headers of the keypoint descriptors satisfying one or more matching criteria are determined, distance determination operations are performed between the keypoint descriptors while the remaining keypoint descriptors are discarded without determining their distances.

公开(公告)号：US20240069957A1

公开(公告)日：2024-02-29

申请号：US18361616

申请日：2023-07-28

Applicant: Apple Inc.

Inventor： Liran FISHEL ,  Erik K. Norden

IPC: G06F9/48 ,  G06F9/54 ,  G06F13/16 ,  G06F13/28 ,  G06N3/045 ,  G06N3/063

CPC classification number: G06F9/4843 ,  G06F9/544 ,  G06F13/1673 ,  G06F13/28 ,  G06N3/045 ,  G06N3/063

Abstract: Embodiments relate to managing tasks that when executed by a neural processor circuit instantiates a neural network. A neural task manager circuit within the neural processor circuit can switch between tasks in different task queues. Each task queue is configured to store a reference to a task list of tasks for instantiating a neural network. Each task queue can also be assigned a priority parameter. While the neural processor circuit is executing tasks of a first task list and prior to completion of each task, the neural task manager circuit can switch between task queues according to the priority parameters for execution of tasks of a second task list by the neural processor circuit. The neural processor circuit includes one or more neural engine circuits that are configured to perform neural operations by executing the tasks assigned by the task manager.