公开(公告)号：US20230359259A1

公开(公告)日：2023-11-09

申请号：US18351248

申请日：2023-07-12

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3287 ,  G06F1/3209

CPC classification number: G06F1/3209 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/00

Abstract: An integrated circuit may include multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances.

公开(公告)号：US10401938B1

公开(公告)日：2019-09-03

申请号：US15483178

申请日：2017-04-10

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Ramesh B. Gunna ,  Shih-Chieh R. Wen ,  John H. Mylius

IPC: G06F1/00 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296

Abstract: Systems, apparatuses, and methods for reaching power targets across different clock domains are described. In various embodiments, a first processor complex and a second processor complex operate while powered by a same, single power plane, but with respective clock domains. When a request is detected to change an operating mode of a particular core from one of the processor complexes to an operating mode which does not provide the worst-case power supply load on the single power plane, an amount of voltage margin to recover from the operational voltage is determined based on the second operating mode prior to granting the request and based on each other core in the complexes operating in respective current operating modes. An operational voltage less the determined voltage margin to recover is assigned to the processor complexes while different clock frequencies are assigned to the processor complexes.

公开(公告)号：US20140215190A1

公开(公告)日：2014-07-31

申请号：US13750942

申请日：2013-01-25

Applicant: APPLE INC.

Inventor： John H. Mylius ,  Rajat Goel ,  Pradeep Kanapathipillai ,  Hari S. Kannan

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3855

Abstract: Techniques are disclosed relating to completion of load and store instructions in a weakly-ordered memory model. In one embodiment, a processor includes a load queue and a store queue and is configured to associate queue information with a load instruction in an instruction stream. In this embodiment, the queue information indicates a location of the load instruction in the load queue and one or more locations in the store queue that are associated with one or more store instructions that are older than the load instruction. The processor may determine, using the queue information, that the load instruction does not conflict with a store instruction in the store queue that is older than the load instruction. The processor may remove the load instruction from the load queue while the store instruction remains in the store queue. The queue information may include a wrap value for the load queue.

Abstract translation: 公开了在弱有序存储器模型中完成负载和存储指令的技术。 在一个实施例中，处理器包括加载队列和存储队列，并且被配置为将队列信息与指令流中的加载指令相关联。 在该实施例中，队列信息指示加载队列中的加载指令的位置和存储队列中与一个或多个比加载指令更早的存储指令相关联的一个或多个位置。 处理器可以使用队列信息来确定加载指令不与存储队列中比加载指令更早的存储指令冲突。 当存储指令保留在存储队列中时，处理器可以从加载队列中移除加载指令。 队列信息可以包括加载队列的换行值。

公开(公告)号：US20140215188A1

公开(公告)日：2014-07-31

申请号：US13749999

申请日：2013-01-25

Applicant: APPLE INC.

Inventor： John H. Mylius ,  Gerard R. Williams, III ,  Shyam Sundar Balasubramanian ,  Conrado Blasco-Allue

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/30145 ,  G06F9/4881 ,  G06F9/4887

Abstract: In an embodiment, a processor includes a multi-level dispatch circuit configured to supply operations for execution by multiple parallel execution pipelines. The multi-level dispatch circuit may include multiple dispatch buffers, each of which is coupled to multiple reservation stations. Each reservation station may be coupled to a respective execution pipeline and may be configured to schedule instruction operations (ops) for execution in the respective execution pipeline. The sets of reservation stations coupled to each dispatch buffer may be non-overlapping. Thus, if a given op is to be executed in a given execution pipeline, the op may be sent to the dispatch buffer which is coupled to the reservation station that provides ops to the given execution pipeline.

Abstract translation: 在一个实施例中，处理器包括被配置为提供由多个并行执行管线执行的操作的多级调度电路。 多级调度电路可以包括多个调度缓冲器，每个调度缓冲器耦合到多个保留站。 每个保留站可以耦合到相应的执行流水线，并且可以被配置为调度用于在相应的执行流水线中执行的指令操作（op）。 耦合到每个调度缓冲器的保留站组可以是不重叠的。 因此，如果在给定的执行流水线中执行给定的操作，则操作可以被发送到调度缓冲器，该调度缓冲器耦合到向给定的执行流水线提供操作的保留站。

公开(公告)号：US11740676B2

公开(公告)日：2023-08-29

申请号：US17821394

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/00 ,  G06F1/3209 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287

CPC classification number: G06F1/3209 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/00

Abstract: An integrated circuit may include multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g., to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

公开(公告)号：US11422606B2

公开(公告)日：2022-08-23

申请号：US17177521

申请日：2021-02-17

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/00 ,  G06F1/3209 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287

Abstract: An integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

公开(公告)号：US09606605B2

公开(公告)日：2017-03-28

申请号：US14200216

申请日：2014-03-07

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/32

CPC classification number: G06F1/3209 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

公开(公告)号：US09336003B2

公开(公告)日：2016-05-10

申请号：US13749999

申请日：2013-01-25

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Gerard R. Williams, III ,  Shyam Sundar Balasubramanian ,  Conrado Blasco-Allue

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/3836 ,  G06F9/30145 ,  G06F9/4881 ,  G06F9/4887

Abstract: In an embodiment, a processor includes a multi-level dispatch circuit configured to supply operations for execution by multiple parallel execution pipelines. The multi-level dispatch circuit may include multiple dispatch buffers, each of which is coupled to multiple reservation stations. Each reservation station may be coupled to a respective execution pipeline and may be configured to schedule instruction operations (ops) for execution in the respective execution pipeline. The sets of reservation stations coupled to each dispatch buffer may be non-overlapping. Thus, if a given op is to be executed in a given execution pipeline, the op may be sent to the dispatch buffer which is coupled to the reservation station that provides ops to the given execution pipeline.

Abstract translation: 在一个实施例中，处理器包括被配置为提供由多个并行执行管线执行的操作的多级调度电路。 多级调度电路可以包括多个调度缓冲器，每个调度缓冲器耦合到多个保留站。 每个保留站可以耦合到相应的执行流水线，并且可以被配置为调度用于在相应的执行流水线中执行的指令操作（op）。 耦合到每个调度缓冲器的保留站组可以是不重叠的。 因此，如果在给定的执行流水线中执行给定的操作，则操作可以被发送到调度缓冲器，该调度缓冲器耦合到向给定的执行流水线提供操作的保留站。

公开(公告)号：US20250093936A1

公开(公告)日：2025-03-20

申请号：US18970560

申请日：2024-12-05

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/3209 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296

Abstract: A system include multiple components configured to operate in different modes with different power supply loads. Control circuitry may determine a first voltage margin to be included in a power supply voltage magnitude requested for the components based on current operating modes of the multiple components and detect that a first component of the multiple components has changed its operating mode. In response to the detection, the control circuitry may modify at least one parameter of the following parameters to recover a portion of the first voltage margin: a power supply voltage magnitude and an operating frequency of at least a portion of the system. A magnitude of the modification may be based on an estimated difference between a first amount of dynamic power supply voltage loss before the change in operating mode and a second amount of dynamic power supply voltage loss after the change in operating mode.

公开(公告)号：US10990159B2

公开(公告)日：2021-04-27

申请号：US15496290

申请日：2017-04-25

Applicant: Apple Inc.

Inventor： Bernard Joseph Semeria ,  John H. Mylius ,  Pradeep Kanapathipillai ,  Richard F. Russo ,  Shih-Chieh Wen ,  Richard H. Larson

IPC: G06F9/38 ,  G06F3/06 ,  G06F1/3287 ,  G06F1/3228 ,  G06F1/3206 ,  G06F1/3296

Abstract: Systems, apparatuses, and methods for retaining architected state for relatively frequent switching between sleep and active operating states are described. A processor receives an indication to transition from an active state to a sleep state. The processor stores a copy of a first subset of the architected state information in on-die storage elements capable of retaining storage after power is turned off. The processor supports programmable input/output (PIO) access of particular stored information during the sleep state. When a wakeup event is detected, circuitry within the processor is powered up again. A boot sequence and recovery of architected state from off-chip memory are not performed. Rather than fetch from a memory location pointed to by a reset base address register, the processor instead fetches an instruction from a memory location pointed to by a restored program counter of the retained subset of the architected state information.