公开(公告)号：US09368416B2

公开(公告)日：2016-06-14

申请号：US13868540

申请日：2013-04-23

Applicant: Apple Inc.

Inventor： Preminder Singh ,  Date Jan Willem Noorlag ,  Sung Wook Kang

IPC: G01N37/00 ,  H01L21/66

CPC classification number: H01L22/20 ,  H01L22/14

Abstract: A binning process uses curve fitting to create and assign one or more bins based on testing data of operating voltage versus leakage current for test integrated circuits. Each bin is created by assigning an initial operating voltage to the bin and fitting a curve to the testing data population. An equation is generated describing the fitted curve. Integrated circuits are binned by measuring the leakage current at a selected operating voltage and testing the integrated circuit at one or more operating voltages determined based on the fitted curves. The integrated circuits are assigned a maximum operating voltage that corresponds to the lowest tested operating voltage at which the integrated circuit passes the test.

Abstract translation: 合并过程使用曲线拟合来创建和分配一个或多个基于测试集成电路的工作电压与泄漏电流的测试数据。 每个仓是通过将初始工作电压分配给仓并将曲线拟合到测试数据群来创建的。 生成描述拟合曲线的方程式。 集成电路通过测量所选工作电压下的漏电流并在基于拟合曲线确定的一个或多个工作电压下测试集成电路进行分组。 分配集成电路的最大工作电压对应于集成电路通过测试的最低测试工作电压。

公开(公告)号：US08912584B2

公开(公告)日：2014-12-16

申请号：US13658049

申请日：2012-10-23

Applicant: Apple Inc.

Inventor： Date Jan Willem Noorlag

IPC: H01L27/146

CPC classification number: H01L27/092 ,  H01L21/823443 ,  H01L21/82345 ,  H01L27/0207 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/78

Abstract: A semiconductor device includes a PFET transistor (a PMOS FET) having a poly(silicon) layer with a p-type doped portion and an n-type doped portion. The p-type doped portion is located above a channel region of the transistor and the n-type doped portion is located in an end portion of the poly layer outside the channel region. The poly layer may be formed by doping portions of an amorphous silicon layer with either the p-type dopant or the n-type dopant and then annealing the amorphous silicon layer to diffuse the dopants and crystallize the amorphous silicon to form polysilicon. The n-type doped portion of the poly layer may provide an electrical shunt in the end portion of the poly layer to reduce any effects of insufficient diffusion of the p-type dopant in the poly layer.

Abstract translation: 半导体器件包括具有p型掺杂部分的多（硅）层和n型掺杂部分的PFET晶体管（PMOS FET）。 p型掺杂部位于晶体管的沟道区域的上方，n型掺杂部位于沟道区域外侧的多晶硅层的端部。 可以通过用p型掺杂剂或n型掺杂剂掺杂非晶硅层的部分来形成多晶硅层，然后使非晶硅层退火以扩散掺杂剂并使非晶硅结晶以形成多晶硅。 多层的n型掺杂部分可以在多层的端部中提供电分流，以减少p型掺杂剂在多层中的扩散不充分的影响。

公开(公告)号：US20140110792A1

公开(公告)日：2014-04-24

申请号：US13658049

申请日：2012-10-23

Applicant: APPLE INC.

Inventor： Date Jan Willem Noorlag

IPC: H01L27/092 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/823443 ,  H01L21/82345 ,  H01L27/0207 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/78

Abstract: A semiconductor device includes a PFET transistor (a PMOS FET) having a poly(silicon) layer with a p-type doped portion and an n-type doped portion. The p-type doped portion is located above a channel region of the transistor and the n-type doped portion is located in an end portion of the poly layer outside the channel region. The poly layer may be formed by doping portions of an amorphous silicon layer with either the p-type dopant or the n-type dopant and then annealing the amorphous silicon layer to diffuse the dopants and crystallize the amorphous silicon to form polysilicon. The n-type doped portion of the poly layer may provide an electrical shunt in the end portion of the poly layer to reduce any effects of insufficient diffusion of the p-type dopant in the poly layer.

Abstract translation: 半导体器件包括具有p型掺杂部分的多（硅）层和n型掺杂部分的PFET晶体管（PMOS FET）。 p型掺杂部位于晶体管的沟道区域的上方，n型掺杂部位于沟道区域外侧的多晶硅层的端部。 可以通过用p型掺杂剂或n型掺杂剂掺杂非晶硅层的部分来形成多晶硅层，然后使非晶硅层退火以扩散掺杂剂并使非晶硅结晶以形成多晶硅。 多层的n型掺杂部分可以在多层的端部中提供电分流，以减少p型掺杂剂在多层中的扩散不充分的影响。

公开(公告)号：US20140316731A1

公开(公告)日：2014-10-23

申请号：US13868540

申请日：2013-04-23

Applicant: APPLE INC.

Inventor： Preminder Singh ,  Date Jan Willem Noorlag ,  Sung Wook Kang

IPC: H01L21/66

CPC classification number: H01L22/20 ,  H01L22/14

Abstract: A binning process uses curve fitting to create and assign one or more bins based on testing data of operating voltage versus leakage current for test integrated circuits. Each bin is created by assigning an initial operating voltage to the bin and fitting a curve to the testing data population. An equation is generated describing the fitted curve. Integrated circuits are binned by measuring the leakage current at a selected operating voltage and testing the integrated circuit at one or more operating voltages determined based on the fitted curves. The integrated circuits are assigned a maximum operating voltage that corresponds to the lowest tested operating voltage at which the integrated circuit passes the test.

Abstract translation: 合并过程使用曲线拟合来创建和分配一个或多个基于测试集成电路的工作电压与泄漏电流的测试数据。 每个仓是通过将初始工作电压分配给仓并将曲线拟合到测试数据群来创建的。 生成描述拟合曲线的方程式。 集成电路通过测量所选工作电压下的漏电流并在基于拟合曲线确定的一个或多个工作电压下测试集成电路进行分组。 分配集成电路的最大工作电压对应于集成电路通过测试的最低测试工作电压。