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    RELAXED INVALIDATION FOR CACHE COHERENCE
    3.
    发明公开
    RELAXED INVALIDATION FOR CACHE COHERENCE 审中-公开

    公开(公告)号：US20230195628A1

    公开(公告)日：2023-06-22

    申请号：US17558034

    申请日：2021-12-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Akhil Arunkumar ,  Tarun Nakra ,  Maxim V. Kazakov ,  Milind N. Nemlekar

    IPC: G06F12/0811 ,  G06F12/0853 ,  G06F13/16

    CPC classification number: G06F12/0811 ,  G06F12/0853 ,  G06F13/1642 ,  G06F13/1668

    Abstract: Methods, systems, and devices maintain state information in a shadow tag memory for a plurality of cachelines in each of a plurality of private caches, with each of the private caches being associated with a corresponding one of multiple processing cores. One or more cache probes are generated based on a write operation associated with one or more cachelines of the plurality of cachelines, such that each of the cache probes is associated with cachelines of a particular private cache of the multiple private caches, the particular private cache being associated with an indicated processing core. Transmission of the cache probes to the particular private cache is prevented until, responsive to a scope acquire operation from the indicated processing core, the cache probes are released for transmission to the respectively associated cachelines in the particular private cache.

    Cache prefetching with dynamic interleaving configuration modification
    4.
    发明授权
    Cache prefetching with dynamic interleaving configuration modification 有权

    公开(公告)号：US11580025B1

    公开(公告)日：2023-02-14

    申请号：US17490529

    申请日：2021-09-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Tarun Nakra ,  Akhil Arunkumar ,  Vydhyanathan Kalyanasundharam ,  Chintan S. Patel ,  Nithesh Kurella Lakshmi Narayanamurthy

    IPC: G06F12/0862

    Abstract: Systems and methods for coordinated memory-side cache prefetching and dynamic interleaving configuration modification involve modifying one or both of the prefetch distance or the prefetch degree used by prefetcher modules of one or more memory-side caches by modifying interleaving configuration data following detection of an interleaving reconfiguration trigger condition indicative, for example, of low prefetch accuracy, low prefetch coverage, high prefetch lateness, or a combination of these. In response an interleaving reconfiguration trigger condition, a processor modifies the interleaving configuration data for the processing system based on the prefetch performance characteristics associated with the interleaving reconfiguration trigger condition. In some embodiments, the interleaving configuration data is modified by changing which physical memory address indices are used to determine the bits that define the channel identification number to which that physical memory address is to be mapped.

    Relaxed invalidation for cache coherence
    5.
    发明授权
    Relaxed invalidation for cache coherence 有权

    公开(公告)号：US11960399B2

    公开(公告)日：2024-04-16

    申请号：US17558034

    申请日：2021-12-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Akhil Arunkumar ,  Tarun Nakra ,  Maxim V. Kazakov ,  Milind N. Nemlekar

    IPC: G06F12/0811 ,  G06F12/0853 ,  G06F13/16

    CPC classification number: G06F12/0811 ,  G06F12/0853 ,  G06F13/1642 ,  G06F13/1668

    Abstract: Methods, systems, and devices maintain state information in a shadow tag memory for a plurality of cachelines in each of a plurality of private caches, with each of the private caches being associated with a corresponding one of multiple processing cores. One or more cache probes are generated based on a write operation associated with one or more cachelines of the plurality of cachelines, such that each of the cache probes is associated with cachelines of a particular private cache of the multiple private caches, the particular private cache being associated with an indicated processing core. Transmission of the cache probes to the particular private cache is prevented until, responsive to a scope acquire operation from the indicated processing core, the cache probes are released for transmission to the respectively associated cachelines in the particular private cache.

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