公开(公告)号：US09684742B1

公开(公告)日：2017-06-20

申请号：US12803097

申请日：2010-06-18

Applicant: Navid Azizi ,  Joshua David Fender ,  Ryan Fung

Inventor： Navid Azizi ,  Joshua David Fender ,  Ryan Fung

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5031 ,  G06F17/504 ,  G06F2217/84

Abstract: A method for performing timing analysis on calibrated paths includes performing static timing analysis on the calibrated paths to obtain delay and margin information. The delay and margin information are utilized to emulate operations performed during calibration.

公开(公告)号：US08281274B1

公开(公告)日：2012-10-02

申请号：US12655864

申请日：2010-01-08

Applicant: Ketan Padalia ,  Ryan Fung

Inventor： Ketan Padalia ,  Ryan Fung

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5022

Abstract: A method for designing a system on a target device includes identifying candidate portions in the system to preserve based on similarities between the system and another system. Preservation criteria are applied on the candidate portions in the system to preserve to identify portions of the system to preserve. Design results from the another system are reused for portions in the system that are preserved.

Abstract translation: 用于在目标设备上设计系统的方法包括基于系统与另一系统之间的相似性来识别系统中的候选部分。 保存标准被应用于系统中的候选部分以保留以标识要保存的系统的部分。 来自另一个系统的设计结果重新用于系统中保留的部分。

公开(公告)号：US08248110B1

公开(公告)日：2012-08-21

申请号：US13048241

申请日：2011-03-15

Applicant: Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz ,  Marcel A. LeBlanc

Inventor： Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz ,  Marcel A. LeBlanc

IPC: H01H71/22

CPC classification number: G06F1/10

Abstract: Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A storage circuit stores an enable signal in response to an output clock signal of the multiplexer. A logic circuit transmits the output clock signal of the multiplexer to a clock routing network in response to the enable signal from the storage circuit. At least one signal is transmitted from the clock switch-over circuit to the control circuit.

Abstract translation: 时钟切换电路和方法为时钟路由网络提供时钟信号。 根据一个实施例，多路复用器响应于从控制电路接收的开关选择信号在第一时钟信号和第二时钟信号之间进行选择。 存储电路响应于多路复用器的输出时钟信号而存储使能信号。 响应于来自存储电路的使能信号，逻辑电路将多路复用器的输出时钟信号传输到时钟路由网络。 至少一个信号从时钟切换电路发送到控制电路。

公开(公告)号：US08185714B1

公开(公告)日：2012-05-22

申请号：US13225468

申请日：2011-09-04

Applicant: Ryan Fung

Inventor： Ryan Fung

IPC: G06F13/00

CPC classification number: G11C7/22 ,  G06F5/06

Abstract: A source-synchronous capture unit includes a data register unit to register data synchronized to a strobe or non-free running clock. The source synchronous capture unit also includes an asynchronous first-in-first-out (FIFO) unit to store the data from the data register unit in response to the strobe or non-free running clock and to output the data stored, in response to another clock.

Abstract translation: 源同步捕获单元包括数据寄存器单元，用于寄存与选通或非自由运行时钟同步的数据。 源同步捕获单元还包括异步先进先出（FIFO）单元，以响应于选通或非自由运行时钟存储来自数据寄存器单元的数据，并响应于 另一个时钟

公开(公告)号：US07977975B1

公开(公告)日：2011-07-12

申请号：US12563088

申请日：2009-09-18

Applicant: David Lewis ,  Jeffrey Christopher Chromczak ,  Ryan Fung

Inventor： David Lewis ,  Jeffrey Christopher Chromczak ,  Ryan Fung

IPC: H03K19/00

CPC classification number: H03K3/356008 ,  H03K3/0375 ,  H03K19/00315 ,  H03K19/17764

Abstract: An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.

Abstract translation: 集成电路（IC）包括一组亚稳态硬化存储电路。 每个亚硬化存储电路可以包括：（a）脉冲宽度失真电路; （b）由标称电源电压供电的第一电路和由高于标称电源电压供电的第二电路; （c）逆变器和偏置电路，其中所述偏置电路基于所述逆变器的中间状态提供偏置电流以解决所述逆变器的亚稳态; 或（d）锁存器和动态偏置电路，其使电流注入到锁存器中以解决闩锁的亚稳态。

公开(公告)号：US07712067B1

公开(公告)日：2010-05-04

申请号：US11879912

申请日：2007-07-19

Applicant: Ryan Fung ,  Michael Chan

Inventor： Ryan Fung ,  Michael Chan

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: A method for connecting a first and second component in a logic device is disclosed. A path is generated between the first and second components with an appropriate amount of delay to satisfy short-path timing constraints that define a minimum delay on the path. A first interconnect line from a plurality of interconnect lines and a second interconnect line to connect with the first interconnect line sub-optimally from a delay minimization perspective are selected in order to satisfy the short-path timing constraints.

Abstract translation: 公开了一种在逻辑器件中连接第一和第二部件的方法。 在第一和第二分量之间产生具有适当延迟量的路径以满足在路径上定义最小延迟的短路时序约束。 选择来自多个互连线的第一互连线和从延迟最小化角度次优化地与第一互连线连接的第二互连线，以便满足短路时序约束。

公开(公告)号：US07694256B1

公开(公告)日：2010-04-06

申请号：US11899097

申请日：2007-09-04

Applicant: David Galloway ,  Ryan Fung

Inventor： David Galloway ,  Ryan Fung

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5054 ,  G06F17/5072 ,  G06F2217/64

Abstract: A method for designing a system on a target device having restricted areas includes determining locations on the target device for all cells in the system by solving one or more equations. Partitioning of cells of a first classification type is performed. One or more equations are modified in response to the partitioning. Revised locations on the target device are determined for the cells by solving the modified one or more equations. The partitioning procedure takes into consideration the classification types of cells as well as restricted areas on the target device.

Abstract translation: 用于在具有受限区域的目标设备上设计系统的方法包括通过求解一个或多个等式来确定目标设备上系统中所有单元的位置。 执行第一分类类型的单元的分区。 响应于分区修改一个或多个等式。 通过求解修正的一个或多个方程，为单元确定目标设备上的修正位置。 分区过程考虑到目标设备上的小区的分类类型以及限制区域。

公开(公告)号：US07659764B2

公开(公告)日：2010-02-09

申请号：US12212314

申请日：2008-09-17

Applicant: Ryan Fung ,  Vaughn Betz

Inventor： Ryan Fung ,  Vaughn Betz

IPC: H03K3/00

CPC classification number: H03K19/17736 ,  H03K5/133 ,  H03K19/1778 ,  H03K19/17792 ,  H03K2005/00058 ,  H03K2005/00234

Abstract: Circuits, methods, and apparatus for delaying signals in a power and area efficient manner are provided. A gating element within a stage of a programmable delay element suppresses an operation of other stages of the delay element. A programmable delay has components with differing delays that may be combined to give flexibility in choices for delay increments while minimizing the area of the delay element. A delay element is shared between different signal paths, for example, to reduce the number of delay elements or to allow utilizing unused delay elements of other signal paths.

Abstract translation: 提供了用于以功率和区域有效的方式延迟信号的电路，方法和装置。 可编程延迟元件的级内的门控元件抑制延迟元件的其他级的操作。 可编程延迟具有不同延迟的组件，其可以组合以在延迟增量的选择中提供灵活性，同时最小化延迟元件的面积。 延迟元件在不同的信号路径之间被共享，例如，以减少延迟元件的数量或允许利用其他信号路径的未使用的延迟元件。

公开(公告)号：US08930175B1

公开(公告)日：2015-01-06

申请号：US13368587

申请日：2012-02-08

Applicant: Ryan Fung

Inventor： Ryan Fung

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5054 ,  G06F17/509 ,  G06F2217/84

Abstract: A method for designing a system on a target device includes performing timing analysis at an intermediate node on a data path from a source to a destination to determine whether rise and fall skew of components on the data path could result in data not being sampled at the destination.

Abstract translation: 用于在目标设备上设计系统的方法包括在从源到目的地的数据路径上的中间节点执行定时分析，以确定数据路径上的组件的上升和下降偏移是否可能导致数据未被采样的数据 目的地。

公开(公告)号：US08775701B1

公开(公告)日：2014-07-08

申请号：US13151272

申请日：2011-06-01

Applicant: Ryan Fung

Inventor： Ryan Fung

IPC: G06F3/00 ,  H04L7/00 ,  H04L7/02 ,  H04L7/04 ,  H04L25/38 ,  G11C7/00 ,  G11C8/00 ,  G06F13/00

CPC classification number: G06F1/12 ,  G06F13/4243 ,  G11C7/1072

Abstract: A source-synchronous capture unit on a receiving circuit includes a first first-in-first-out (FIFO) unit operable to synchronize a write enable signal to generate a synchronized write enable signal that is synchronized with a first free running clock associated with a memory external to the receiving circuit. The write enable sign is generated in response to a read operation by the receiving circuit. The source-synchronous capture unit also includes a second FIFO unit operable to store data from the memory in response to the first free running clock and the synchronized write enable signal, and to output the data in response to a second free running clock associated with the receiving circuit and a read enable signal.

Abstract translation: 接收电路上的源同步捕获单元包括第一先进先出（FIFO）单元，其可操作以使写使能信号同步，以产生与第一自由运行时钟同步的同步写使能信号，该第一自由运行时钟与 接收电路外部的存储器。 响应于接收电路的读取操作产生写入使能符号。 源同步捕获单元还包括第二FIFO单元，其可操作以响应于第一自由运行时钟和同步的写入使能信号来存储来自存储器的数据，并且响应于与第二自由运行时钟相关联的第二自由运行时钟输出数据 接收电路和读使能信号。