公开(公告)号：US08577489B2

公开(公告)日：2013-11-05

申请号：US13014152

申请日：2011-01-26

Applicant: James A. Bruce ,  Kenneth T. Settlemyer, Jr.

Inventor： James A. Bruce ,  Kenneth T. Settlemyer, Jr.

IPC: G06F19/00

CPC classification number: G03F1/36 ,  G03F1/70 ,  G03F7/705

Abstract: Solutions for diagnosing in-line critical dimension control adjustments in a lithographic process are disclosed. In one embodiment, a method includes: locating a control structure in a data set representing one of a chip or a kerf; simulating component dimensions within a region proximate to the control structure; determining a difference between the simulated component dimensions within the region and target component dimensions within the region; determining whether the difference exceeds a predetermined tolerance threshold; adjusting a simulation condition in response to determining the difference exceeds the predetermined tolerance threshold; and repeating the simulating of the component dimensions within the region, the determining of the difference, and the determining of whether the difference exceeds the predetermined tolerance threshold in response to the adjusting of the simulation condition.

Abstract translation: 公开了用于诊断光刻工艺中的在线临界尺寸控制调整的解决方案。 在一个实施例中，一种方法包括：将控制结构定位在表示芯片或切口之一的数据集中; 在靠近控制结构的区域内模拟部件尺寸; 确定区域内的模拟部件尺寸与该区域内的目标部件尺寸之间的差异; 确定所述差异是否超过预定的容差阈值; 响应于确定所述差异来调整模拟条件超过所述预定公差阈值; 并且响应于所述模拟条件的调整，重复所述区域内的所述分量尺寸的模拟，所述差的确定以及所述差是否超过所述预定公差阈值。

公开(公告)号：US20080261128A1

公开(公告)日：2008-10-23

申请号：US12106586

申请日：2008-04-21

Applicant: Deok-kee Kim ,  Kenneth T. Settlemyer ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Thimothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

Inventor： Deok-kee Kim ,  Kenneth T. Settlemyer ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Thimothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

IPC: G03F7/004 ,  G03F7/20

CPC classification number: H01L21/0337 ,  G03F7/11 ,  H01L21/027 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0338 ,  H01L21/31144

Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

Abstract translation: 增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。 提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。 这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

公开(公告)号：US07390745B2

公开(公告)日：2008-06-24

申请号：US11162800

申请日：2005-09-23

Applicant: Thomas W. Dyer ,  Kenneth T. Settlemyer, Jr. ,  James J. Toomey ,  Haining Yang

Inventor： Thomas W. Dyer ,  Kenneth T. Settlemyer, Jr. ,  James J. Toomey ,  Haining Yang

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/30608 ,  H01L21/32134

Abstract: A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.

Abstract translation: 与使用本发明的方法形成的结构一起设置在具有基本均匀的直边或边缘以及良好限定的内角和外角的含Si结晶材料中产生预定形状的方法。 本发明的方法利用常规的光刻和蚀刻将图案（即形状）转移到含结晶的含Si材料。 由于使用了常规处理，所以图案具有圆角的固有限制。 使用利用稀释氢氧化铵溶液的选择性蚀刻方法来消除圆角，提供具有基本上直的边或边缘和基本上圆角的最终形状。

公开(公告)号：US20120192124A1

公开(公告)日：2012-07-26

申请号：US13014159

申请日：2011-01-26

Applicant: JAMES A. BRUCE ,  KENNETH T. SETTLEMYER, JR.

Inventor： JAMES A. BRUCE ,  KENNETH T. SETTLEMYER, JR.

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F7/70441

Abstract: Solutions for accounting for photomask deviations in a lithographic process during optical proximity correction verification are disclosed. In one embodiment, a method includes: identifying a wafer control structure in a data set representing one of a first chip or a kerf; biasing the data set representing the first chip in the case that the wafer control structure is in the data set representing the first chip; biasing the data set representing the kerf or a second chip distinct from the first chip, in the case that the wafer control structure is in the data set representing the kerf or the second chip; simulating formation of the wafer control structure; determining whether the simulated wafer control structure complies with a target control structure; and iteratively adjusting an exposure dose condition in the case that the simulated wafer control structure does not comply with the target control structure.

Abstract translation: 公开了在光学邻近校正验证期间在光刻工艺中考虑光掩模偏差的解决方案。 在一个实施例中，一种方法包括：识别表示第一芯片或切口之一的数据集中的晶片控制结构; 在晶片控制结构处于表示第一芯片的数据集的情况下，偏置表示第一芯片的数据组; 在晶片控制结构处于表示切口或第二芯片的数据组的情况下，偏置表示切口的数据组或不同于第一芯片的第二芯片; 模拟晶圆控制结构的形成; 确定模拟晶片控制结构是否符合目标控制结构; 并且在模拟晶片控制结构不符合目标控制结构的情况下，迭代地调整曝光剂量条件。

公开(公告)号：US07718993B2

公开(公告)日：2010-05-18

申请号：US12108574

申请日：2008-04-24

Applicant: Thomas W. Dyer ,  Kenneth T. Settlemyer ,  James J. Toomey ,  Haining Yang

Inventor： Thomas W. Dyer ,  Kenneth T. Settlemyer ,  James J. Toomey ,  Haining Yang

IPC: H01L31/00

CPC classification number: H01L21/30608 ,  H01L21/32134

Abstract: A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.

Abstract translation: 与使用本发明的方法形成的结构一起设置在具有基本均匀的直边或边缘以及良好限定的内角和外角的含Si结晶材料中产生预定形状的方法。 本发明的方法利用常规的光刻和蚀刻将图案（即形状）转移到含结晶的含Si材料。 由于使用了常规处理，所以图案具有圆角的固有限制。 使用利用稀释氢氧化铵溶液的选择性蚀刻方法来消除圆角，提供具有基本上直的边或边缘和基本上圆角的最终形状。

公开(公告)号：US07696539B2

公开(公告)日：2010-04-13

申请号：US12141878

申请日：2008-06-18

Applicant: Yujun Li ,  Kenneth T. Settlemyer, Jr. ,  Jochen Beintner

Inventor： Yujun Li ,  Kenneth T. Settlemyer, Jr. ,  Jochen Beintner

IPC: H01L29/80

CPC classification number: H01L21/84 ,  H01L21/30608 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66772 ,  H01L29/66818 ,  H01L29/785

Abstract: A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.

Abstract translation: 提出了一种制造方法和场效应器件结构，其减少源/漏电容并允许器件接触。 产生基于Si的材料基座，其顶表面和其侧壁的方向定位成与基座和支撑构件的选定结晶平面基本平行。 用包含氢氧化铵的各向异性溶液湿式蚀刻基座。 基座的侧壁变小，在基座上形成截面减小的部分。 选择减小的横截面段中的掺杂剂浓度足够高以使其提供穿过基座的电连续性。

公开(公告)号：US07563670B2

公开(公告)日：2009-07-21

申请号：US11558974

申请日：2006-11-13

Applicant: Kangguo Cheng ,  Richard O. Henry ,  Kenneth T. Settlemyer, Jr.

Inventor： Kangguo Cheng ,  Richard O. Henry ,  Kenneth T. Settlemyer, Jr.

IPC: H01L21/8242 ,  H01L21/336 ,  H01L21/20

CPC classification number: H01L21/32134 ,  H01L21/30608 ,  H01L27/10841 ,  H01L27/10864

Abstract: A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the upper trench portion beyond the exposed upper surface of the semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer.

Abstract translation: 一种形成垂直DRAM装置的方法。 下沟槽填充有用于电容器的多晶或非晶半导体。 上沟槽部分具有暴露的单晶半导体的侧壁。 该方法然后包括蚀刻单晶半导体侧壁以将上部沟槽部分加宽超过电容器的半导体填充物的暴露的上表面，以在邻近暴露的上部沟槽的上部沟槽的底部上形成单晶半导体的暴露区域 半导体填料的上表面。 沟槽顶部绝缘层沉积在上沟槽的底部上方，半导体填充物的上表面和相邻的单晶半导体区域之上。 该方法然后包括形成垂直栅极电介质层，其中沟槽顶部绝缘层延伸到垂直栅极绝缘层下方。

公开(公告)号：US07122439B2

公开(公告)日：2006-10-17

申请号：US10904582

申请日：2004-11-17

Applicant: Oh-Jung Kwon ,  Kenneth T. Settlemyer, Jr. ,  Ravikumar Ramachandran ,  Min-Soo Kim

Inventor： Oh-Jung Kwon ,  Kenneth T. Settlemyer, Jr. ,  Ravikumar Ramachandran ,  Min-Soo Kim

IPC: H01L21/20

CPC classification number: H01L27/1087 ,  H01L29/66181

Abstract: A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench.

Abstract translation: 制造瓶沟槽和瓶沟电容器的方法。 该方法包括：提供衬底; 在所述衬底中形成沟槽，所述沟槽具有侧壁和底部，所述沟槽具有与所述衬底的顶表面相邻的上部区域和与所述沟槽的底部相邻的下部区域; 在沟槽的底部区域形成衬底的氧化层; 并且从沟槽的底部区域去除衬底的氧化层，沟槽的下部区域的横截面面积大于沟槽的上部区域的横截面面积。

公开(公告)号：US06723611B2

公开(公告)日：2004-04-20

申请号：US10241225

申请日：2002-09-10

Applicant: Hiroyuki Akatsu ,  Oleg Gluschenkov ,  Porshia S. Parkinson ,  Ravikumar Ramachandran ,  Helmut Horst Tews ,  Kenneth T. Settlemyer, Jr.

Inventor： Hiroyuki Akatsu ,  Oleg Gluschenkov ,  Porshia S. Parkinson ,  Ravikumar Ramachandran ,  Helmut Horst Tews ,  Kenneth T. Settlemyer, Jr.

IPC: H01L2120

CPC classification number: H01L27/1087

Abstract: In the course of forming a trench capacitor or similar structure, the sidewalls of an aperture in a substrate are lined with a film stack containing a diffusion barrier; an upper portion of the outer layer is stripped, so that the upper and lower portions have different materials exposed; the lower portion of the film stack is stripped while the upper portion is protected by a hardmask layer; a diffusion step is performed in the lower portion while the upper portion is protected; and a selected material such as hemispherical grained silicon is deposited selectively on the lower portion while the exposed surface of the upper portion is a material on which the selected material forms poorly, so that the diffusing material penetrates and the selected material is formed only on the lower portion.

Abstract translation: 在形成沟槽电容器或类似结构的过程中，衬底中的孔的侧壁衬有包含扩散阻挡层的膜堆叠; 外层的上部被剥离，使得上部和下部具有不同的材料暴露; 薄膜堆叠的下部被剥离，同时上部被硬掩模层保护; 在上部被保护的同时在下部进行扩散步骤; 并且选择性地将选择的材料如半球形硅沉积在下部上，而上部的暴露表面是选择的材料形成不良的材料，使得扩散材料渗透，并且所选择的材料仅形成在 下部。

公开(公告)号：US06565666B1

公开(公告)日：2003-05-20

申请号：US09723069

申请日：2000-11-27

Applicant: Russell H. Arndt ,  Glenn Walton Gale ,  Frederick William Kern, Jr. ,  Kenneth T. Settlemyer, Jr. ,  William A. Syverson

Inventor： Russell H. Arndt ,  Glenn Walton Gale ,  Frederick William Kern, Jr. ,  Kenneth T. Settlemyer, Jr. ,  William A. Syverson

IPC: B08B700

CPC classification number: H01L21/67034 ,  Y10S134/902 ,  Y10S438/906 ,  Y10T428/24 ,  Y10T428/24124 ,  Y10T428/24273 ,  Y10T428/24298 ,  Y10T428/24405 ,  Y10T428/24413

Abstract: Disclosed is a method of removing liquid from a surface of a semiconductor wafer that comprises the steps of providing a plurality of capillary channels, each said capillary channel having a first opening and a second opening, and then placing said first openings in contact with the liquid in a manner effective in drawing away the liquid by capillary action.

Abstract translation: 公开了一种从半导体晶片的表面去除液体的方法，包括以下步骤：提供多个毛细通道，每个所述毛细通道具有第一开口和第二开口，然后将所述第一开口与液体接触 以有效地通过毛细作用抽出液体的方式。