FLEXIBLE ETHERNET AND MULTI LINK GEARBOX MAPPING PROCEDURE TO OPTICAL TRANSPORT NETWORK
    1.
    发明申请
    FLEXIBLE ETHERNET AND MULTI LINK GEARBOX MAPPING PROCEDURE TO OPTICAL TRANSPORT NETWORK 审中-公开
    柔性以太网和多连接GEARBOX映射到光传输网络的程序

    公开(公告)号:US20160119075A1

    公开(公告)日:2016-04-28

    申请号:US14564987

    申请日:2014-12-09

    IPC分类号: H04J14/02 H04B10/27

    摘要: A flexible mapping method to map a Physical Coding Sublayer (PCS) structure from Flexible Ethernet and/or Multi Link Gearbox (MLG) to Optical Transport Network (OTN), includes receiving one or more Virtual Lanes; and mapping each of the one or more Virtual Lanes into a Tributary Slot, wherein a rate and number of the Tributary Slot(s) in OTN is set based on a rate and number of the one or more Virtual Lanes. A transport system and a flexible de-mapping method are also described. The systems and methods map the generalized MLG-style group of lanes (virtual PHYs/PMDs) into an OPUflex Tributary Slot (TS) structure, keeping PCS structures intact, and creates a single ODUflex container with a matching rate of FlexE for end-to-end flow.

    摘要翻译: 将物理编码子层(PCS)结构从柔性以太网和/或多链路齿轮箱(MLG)映射到光传输网络(OTN)的灵活映射方法包括:接收一个或多个虚拟车道; 以及将所述一个或多个虚拟通道中的每一个映射到支路插槽,其中基于所述一个或多个虚拟通道的速率和数量来设置OTN中的支路时隙的速率和数量。 还描述了传输系统和灵活的去映射方法。 系统和方法将通用的MLG风格的通道组(虚拟PHY / PMD)映射到OPUflex支路插槽(TS)结构中,保持PCS结构完整,并创建一个具有匹配的FlexE速率的单个ODUflex容器,用于端到端 - 流程。

    Method and apparatus for aligning multiple outputs of an FPGA

    公开(公告)号:US07467056B2

    公开(公告)日:2008-12-16

    申请号:US11716187

    申请日:2007-03-09

    IPC分类号: H04B13/00

    摘要: Each data lane connected to a FPGA and forming part of a SFI channel may be trained independently to enable the outputs from the FPGA to be aligned. In operation, a known fixed pattern is repeated on each of the data lanes with the exception of the data lane being trained. The short fixed pattern is smaller than an SERDES capture range so that the SERDES may temporarily lock onto the short fixed pattern for all data lanes other than the lane being trained. Training data is then transmitted on the lane being trained and the preskew delay for that lane is adjusted until the receiving component indicates that the lanes are aligned. This process may iterate to find acceptable preskew delay values for all lanes. By training the lanes one at a time and using a short repeating pattern on the untrained lanes, the SERDES may register that the untrained lanes are operating correctly so that the feedback from the SERDES is related only to the lane being trained.

    Segmented complex diffraction gratings
    3.
    发明申请
    Segmented complex diffraction gratings 审中-公开
    分段复杂衍射光栅

    公开(公告)号:US20050231804A1

    公开(公告)日:2005-10-20

    申请号:US11145251

    申请日:2005-06-03

    摘要: A structure (i.e. a segmented grating) which applies a designated complex-valued spectral filtering function to the input optical field and emits a filtered version of the input field in an output direction and a method for making such a structure. The segmented gratings fabricated in accordance with the present invention consist of a series of spatially distinct subgratings arrayed end to end. Each subgrating possesses a periodic array of diffraction structures (lines or more general elements). The overall transfer function of the segmented grating is determined by controlling (a) the spatial periodicity or frequency of each subgrating, (b) the amplitude of each subgrating, (c) the spacing between the last diffraction structure (or line) on each subgrating and the first diffraction structure (or line) of the successive subgrating, and (d) the optical path length and transparency through each subgrating, or each subgrating plus additional material layers utilized to control optical path length and transparency.

    摘要翻译: 一种结构(即,分段光栅),其向输入光场施加指定的复值频谱滤波函数,并且在输出方向上发射输入场的滤波版本以及用于制造这种结构的方法。 根据本发明制造的分段光栅由端到端排列的一系列空间上不同的亚格子组成。 每个子格栅具有衍射结构的周期性阵列(线或更一般的元素)。 通过控制(a)每个子格栅的空间周期或频率,(b)每个亚格子化的幅度,(c)每个亚格子化的最后衍射结构(或线)之间的间距来确定分段光栅的总传递函数 以及(d)通过每个亚格子化的光路长度和透明度,或每个亚光加上用于控制光程长度和透明度的附加材料层的第一衍射结构(或线)。

    Using active and passive optical components for an optical network
    4.
    发明授权
    Using active and passive optical components for an optical network 失效
    使用有源和无源光学组件进行光网络

    公开(公告)号:US07433603B2

    公开(公告)日:2008-10-07

    申请号:US10319052

    申请日:2002-12-13

    IPC分类号: H04B7/216 H04J14/02

    CPC分类号: H04L27/2096

    摘要: In one embodiment, the present invention includes a network hub having an active optical encoder where the network hub is to generate a plurality of addressed optical data signals, each having a common carrier wavelength and a different address corresponding to a network node coupled to the network hub. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,本发明包括具有主动光学编码器的网络集线器,其中网络集线器将产生多个寻址光数据信号,每个具有公共载波波长和与耦合到该网络的网络节点对应的不同地址 枢纽。 描述和要求保护其他实施例。

    Method and apparatus for aligning multiple outputs of an FPGA
    5.
    发明申请
    Method and apparatus for aligning multiple outputs of an FPGA 有权
    用于对准FPGA的多个输出的方法和装置

    公开(公告)号:US20080222594A1

    公开(公告)日:2008-09-11

    申请号:US11716187

    申请日:2007-03-09

    IPC分类号: H03K17/693

    摘要: Each data lane connected to a FPGA and forming part of a SFI channel may be trained independently to enable the outputs from the FPGA to be aligned. In operation, a known fixed pattern is repeated on each of the data lanes with the exception of the data lane being trained. The short fixed pattern is smaller than an SERDES capture range so that the SERDES may temporarily lock onto the short fixed pattern for all data lanes other than the lane being trained. Training data is then transmitted on the lane being trained and the preskew delay for that lane is adjusted until the receiving component indicates that the lanes are aligned. This process may iterate to find acceptable preskew delay values for all lanes. By training the lanes one at a time and using a short repeating pattern on the untrained lanes, the SERDES may register that the untrained lanes are operating correctly so that the feedback from the SERDES is related only to the lane being trained.

    摘要翻译: 可以独立地训练连接到FPGA并形成SFI通道的一部分的每个数据通道,以使来自FPGA的输出能够对准。 在操作中,除了正在训练的数据通道之外,在每个数据通道上重复已知的固定模式。 短的固定模式小于SERDES捕获范围,以便SERDES可能暂时锁定到除被训练的通道之外的所有数据通道的短固定模式。 然后训练数据在被训练的车道上传送,并且调整该车道的预定时延,直到接收组件指示车道对齐。 该过程可以迭代以找到所有车道的可接受的前置时间延迟值。 通过一次训练车道并在未经训练的车道上使用短暂的重复模式,SERDES可以注册未经训练的车道正常运行,以便来自SERDES的反馈仅与被训练的车道相关。

    Segmented complex diffraction gratings
    7.
    发明申请
    Segmented complex diffraction gratings 审中-公开
    分段复杂衍射光栅

    公开(公告)号:US20050225860A1

    公开(公告)日:2005-10-13

    申请号:US11144583

    申请日:2005-06-03

    摘要: A structure (i.e. a segmented grating) which applies a designated complex-valued spectral filtering function to the input optical field and emits a filtered version of the input field in an output direction and a method for making such a structure. The segmented gratings fabricated in accordance with the present invention consist of a series of spatially distinct subgratings arrayed end to end. Each subgrating possesses a periodic array of diffraction structures (lines or more general elements). The overall transfer function of the segmented grating is determined by controlling (a) the spatial periodicity or frequency of each subgrating, (b) the amplitude of each subgrating,(c) the spacing between the last diffraction structure (or line) on each subgrating and the first diffraction structure (or line) of the successive subgrating, and (d) the optical path length and transparency through each subgrating, or each subgrating plus additional material layers utilized to control optical path length and transparency.

    摘要翻译: 一种结构(即,分段光栅),其向输入光场施加指定的复值频谱滤波函数,并且在输出方向上发射输入场的滤波版本以及用于制造这种结构的方法。 根据本发明制造的分段光栅由端到端排列的一系列空间上不同的亚格子组成。 每个子格栅具有衍射结构的周期性阵列(线或更一般的元素)。 通过控制(a)每个子格栅的空间周期或频率,(b)每个亚格子化的幅度,(c)每个亚格子化的最后衍射结构(或线)之间的间距来确定分段光栅的总传递函数 以及(d)通过每个亚格子化的光路长度和透明度,或每个亚光加上用于控制光程长度和透明度的附加材料层的第一衍射结构(或线)。