- 专利标题: Device architecture and method for precision enhancement of vertical semiconductor devices
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申请号: US15451074申请日: 2017-03-06
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公开(公告)号: US09997455B2公开(公告)日: 2018-06-12
- 发明人: Thomas E. Harrington, III
- 申请人: D3 Semiconductor LLC
- 申请人地址: US TX Addison
- 专利权人: D3 Semiconductor LLC
- 当前专利权人: D3 Semiconductor LLC
- 当前专利权人地址: US TX Addison
- 代理机构: Schultz & Associates, P.C.
- 主分类号: H01L23/525
- IPC分类号: H01L23/525 ; H01L27/088 ; H01L29/78 ; H01L27/06 ; H01L49/02 ; H01L29/739 ; H01L27/112 ; H01L21/66
摘要:
Improvement of key electrical specifications of vertical semiconductor devices, usually found in the class of devices known as discrete semiconductors, has a direct impact on the performance achievement and power efficiency of the systems in which these devices are used. Imprecise vertical device specifications cause system builders to either screen incoming devices for their required specification targets or to design their system with lower performance or lower efficiency than desired. Disclosed is an architecture and method for achieving a desired target specification for a vertical semiconductor device. Precise trimming of threshold voltage improves targeting of both on-resistance and switching time. Precise trimming of gate resistance also improves targeting of switching time. Precise trimming of a device's effective width improves targeting of both on-resistance and current-carrying capability. Device parametrics are trimmed to improve a single device, or a parametric specification is targeted to match specifications on two or more devices.
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