- 专利标题： Apparatus and method for implementing design for testability (DFT) for bitline drivers of memory circuits
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申请号： US15472121申请日： 2017-03-28
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公开(公告)号： US09947419B1公开(公告)日： 2018-04-17
- 发明人: Rakesh Kumar Sinha , Priyankar Mathuria , Sharad Kumar Gupta
- 申请人： QUALCOMM Incorporated
- 申请人地址： US CA San Diego
- 专利权人： QUALCOMM Incorporated
- 当前专利权人： QUALCOMM Incorporated
- 当前专利权人地址： US CA San Diego
- 代理机构： Loza & Loza, LLP/Qualcomm
- 主分类号： G11C29/50
- IPC分类号： G11C29/50 ; G11C29/12 ; G11C11/419
摘要：
A first bitline driver includes a multiplexer for outputting data and write mask signals in functional mode, and test vector signal in test mode; a latch to latch the data signal in functional mode and the test vector signal in test mode; a latch to latch the write mask signal in functional mode and the test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell based on the data signal. A second bitline driver includes a latch to latch a data signal in functional mode if a write mask signal is deasserted and to latch a test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell.
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