发明授权
- 专利标题: Non-volatile latch circuit and logic circuit, and semiconductor device using the same
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申请号: US13667292申请日: 2012-11-02
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公开(公告)号: US09692421B2公开(公告)日: 2017-06-27
- 发明人: Kiyoshi Kato , Jun Koyama
- 申请人: Semiconductor Energy Laboratory Co., Ltd.
- 申请人地址: JP Atsugi-shi, Kanagawa-ken
- 专利权人: Semiconductor Energy Laboratory Co., Ltd.
- 当前专利权人: Semiconductor Energy Laboratory Co., Ltd.
- 当前专利权人地址: JP Atsugi-shi, Kanagawa-ken
- 代理机构: Fish & Richardson P.C.
- 优先权: JP2009-288146 20091218
- 主分类号: H01L25/00
- IPC分类号: H01L25/00 ; H03K19/00 ; H03K19/173 ; G11C14/00 ; H01L21/8258 ; H01L21/84 ; H01L27/06 ; H01L27/088 ; H01L27/12 ; H01L29/786 ; H03K3/356 ; G11C16/02 ; H01L27/1156
摘要:
A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element through a second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and a capacitor is provided to be electrically connected to a source electrode or a drain electrode of the transistor, whereby data of the latch circuit can be retained, and a non-volatile latch circuit can thus be formed.
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