Invention Grant
- Patent Title: Methods of manufacturing an integrated circuit having stress tuning layer
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Application No.: US15056615Application Date: 2016-02-29
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Publication No.: US09633954B2Publication Date: 2017-04-25
- Inventor: Shin-Puu Jeng , Clinton Chao , Szu Wei Lu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/00 ; H01L21/302 ; H01L21/314 ; H01L21/316 ; H01L21/318 ; H01L23/52 ; H01L21/56 ; H01L21/78 ; H01L23/58

Abstract:
Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.
Public/Granted literature
- US20160181209A1 Integrated Circuit Having Stress Tuning Layer and Methods of Manufacturing Same Public/Granted day:2016-06-23
Information query
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