发明授权
- 专利标题： Method of manufacturing a MISFET on an SOI substrate
- 专利标题（中）： 在SOI衬底上制造MISFET的方法
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申请号： US14929646申请日： 2015-11-02
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公开(公告)号： US09484433B2公开(公告)日： 2016-11-01
- 发明人: Yoshiki Yamamoto , Hideki Makiyama , Toshiaki Iwamatsu , Takaaki Tsunomura
- 申请人： Renesas Electronics Corporation
- 申请人地址： JP Tokyo
- 专利权人： Renesas Electronics Corporation
- 当前专利权人： Renesas Electronics Corporation
- 当前专利权人地址： JP Tokyo
- 代理机构： Shapiro, Gabor and Rosenberger, PLLC
- 优先权： JP2012-011213 20120123; JP2012-163907 20120724
- 主分类号： H01L21/00
- IPC分类号： H01L21/00 ; H01L29/66 ; H01L29/786 ; H01L27/12 ; H01L29/417 ; H01L29/423 ; H01L29/78 ; H01L21/768 ; H01L29/08 ; H01L21/8238 ; H01L21/84 ; H01L21/265
摘要：
Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
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