Invention Grant
US09372499B2 Low insertion delay clock doubler and integrated circuit clock distribution system using same
有权
低插入延迟时钟倍频器和集成电路时钟分配系统使用相同
- Patent Title: Low insertion delay clock doubler and integrated circuit clock distribution system using same
- Patent Title (中): 低插入延迟时钟倍频器和集成电路时钟分配系统使用相同
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Application No.: US14159967Application Date: 2014-01-21
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Publication No.: US09372499B2Publication Date: 2016-06-21
- Inventor: Sriram Sambamurthy , Arun Sundaresan Iyer , Alok Baluni , Aaron Grenat
- Applicant: Advanced Micro Devices, Inc.
- Agency: Polansky & Associates P.L.L.C.
- Agent Paul J. Polansky
- Main IPC: H03B19/00
- IPC: H03B19/00 ; G06F1/04 ; H03K19/20 ; H03K5/00 ; H03K19/00
Abstract:
A clock doubler includes a first NAND gate having a first input for receiving a clock input signal and a second input, a second NAND gate having a first input and a second input for receiving a complement of the clock input signal, an output NAND gate having a first and second inputs coupled to outputs of the first and second NAND gates, respectively, and an output for providing a clock output signal, an inverter chain having an input for receiving the clock input signal and responsive to first and second control signals to selectively provide a first true output to the first input of the second NAND gate, and a second complementary output to the second input of the first NAND gate, and a control signal generation circuit providing the first and second control signals in response to the outputs of the first and second NAND gates.
Public/Granted literature
- US20150205323A1 LOW INSERTION DELAY CLOCK DOUBLER AND INTEGRATED CIRCUIT CLOCK DISTRIBUTION SYSTEM USING SAME Public/Granted day:2015-07-23
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