发明授权
- 专利标题: Parallel bit interleaver
- 专利标题(中): 并行位交织器
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申请号: US14116608申请日: 2012-05-18
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公开(公告)号: US09032260B2公开(公告)日: 2015-05-12
- 发明人: Mihail Petrov
- 申请人: Mihail Petrov
- 申请人地址: JP Osaka
- 专利权人: Panasonic Corporation
- 当前专利权人: Panasonic Corporation
- 当前专利权人地址: JP Osaka
- 代理机构: Wenderoth, Lind & Ponack, L.L.P.
- 优先权: EP11004126 20110518
- 国际申请: PCT/JP2012/003260 WO 20120518
- 国际公布: WO2012/157282 WO 20121122
- 主分类号: G06F11/00
- IPC分类号: G06F11/00 ; H03M13/00 ; H03M13/27 ; H03M13/11 ; H03M13/25 ; H03M13/29 ; H03M13/35 ; H04L1/00
摘要:
A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.
公开/授权文献
- US20140126674A1 PARALLEL BIT INTERLEAVER 公开/授权日:2014-05-08
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