发明授权
- 专利标题: Semiconductor device with overlapped lead terminals
- 专利标题(中): 具有重叠引线端子的半导体器件
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申请号: US12856664申请日: 2010-08-15
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公开(公告)号: US08853865B2公开(公告)日: 2014-10-07
- 发明人: Hiroaki Narita
- 申请人: Hiroaki Narita
- 申请人地址: JP Kawasaki-shi
- 专利权人: Renesas Electronics Corporation
- 当前专利权人: Renesas Electronics Corporation
- 当前专利权人地址: JP Kawasaki-shi
- 代理机构: Miles & Stockbridge P.C.
- 优先权: JP2009-223948 20090929; JP2010-072233 20100326
- 主分类号: H01L23/48
- IPC分类号: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L23/00 ; H01L23/495 ; H01L21/48 ; H01L21/683 ; H01L23/31 ; H01L21/56 ; H05K3/34
摘要:
The size and thickness of a semiconductor device are reduced. A semiconductor package with a flip chip bonding structure includes: a semiconductor chip having a main surface with multiple electrode pads formed therein and a back surface located on the opposite side thereto; four lead terminals each having an upper surface with the semiconductor chip placed thereover and a lower surface located on the opposite side thereto; and a sealing body having a main surface and a back surface located on the opposite side thereto. In this semiconductor package, the distance between adjacent first lower surfaces of the four lead terminals exposed in the back surface of the sealing body is made longer than the distance between adjacent upper surfaces thereof. This makes it possible to suppress the production of a solder bridge when the semiconductor package is solder mounted to a mounting board and to reduce the size and thickness of the semiconductor package and further enhance the reliability of the semiconductor package.
公开/授权文献
- US20110074016A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 公开/授权日:2011-03-31
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