A resistive memory device comprises a memory cell array comprising a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row selector connected to the plurality of word lines, and a column selector connected to the plurality of bit lines. In a program or erase operation, the row selector provides a selected word line with program or erase pulse and a verification pulse in each of multiple program loops, wherein the verification pulse has a substantially fixed level through the program loops and the program or erase pulse has a negative value that decreases incrementally between successive program loops.