Invention Grant
- Patent Title: Nested and isolated transistors with reduced impedance difference
- Patent Title (中): 具有降低阻抗差的嵌套和隔离晶体管
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Application No.: US12848999Application Date: 2010-08-02
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Publication No.: US08143651B2Publication Date: 2012-03-27
- Inventor: Johnny Widodo , Liang Choo Hsia , James Yong Meng Lee , Wen Zhi Gao , Zhao Lun , Huang Liu , Chung Woh Lai , Shailendra Mishra , Yew Tuck Chow , Fang Chen , Shiang Yang Ong
- Applicant: Johnny Widodo , Liang Choo Hsia , James Yong Meng Lee , Wen Zhi Gao , Zhao Lun , Huang Liu , Chung Woh Lai , Shailendra Mishra , Yew Tuck Chow , Fang Chen , Shiang Yang Ong
- Applicant Address: SG Singapore
- Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Current Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Horizon IP Pte Ltd
- Main IPC: H01L27/10
- IPC: H01L27/10 ; H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113 ; H01L31/119
Abstract:
A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.
Public/Granted literature
- US20100301424A1 NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE Public/Granted day:2010-12-02
Information query
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