Invention Grant
US06955969B2 Method of growing as a channel region to reduce source/drain junction capacitance
有权
生长为沟道区域以减少源极/漏极结电容的方法
- Patent Title: Method of growing as a channel region to reduce source/drain junction capacitance
- Patent Title (中): 生长为沟道区域以减少源极/漏极结电容的方法
-
Application No.: US10654497Application Date: 2003-09-03
-
Publication No.: US06955969B2Publication Date: 2005-10-18
- Inventor: Ihsan J. Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold P. Maszara , James N. Pan , Qi Xiang
- Applicant: Ihsan J. Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold P. Maszara , James N. Pan , Qi Xiang
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Föley & Lardner LLP
- Main IPC: H01L21/20
- IPC: H01L21/20 ; H01L29/06 ; H01L29/08 ; H01L29/10 ; H01L29/78 ; H01L21/336 ; H01L21/338
Abstract:
A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, depositing a layer having a first thickness above the oxide layer and the SiGe feature, and forming source and drain regions in the layer.
Public/Granted literature
- US20050048743A1 Method of growing as a channel region to reduce source/drain junction capicitance Public/Granted day:2005-03-03
Information query
IPC分类:
