Invention Grant
- Patent Title: Misfet semiconductor device having different vertical levels
- Patent Title (中): Misfet半导体器件具有不同的垂直电平
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Application No.: US683537Application Date: 1996-07-15
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Publication No.: US6087727APublication Date: 2000-07-11
- Inventor: Toshiaki Tsutsumi
- Applicant: Toshiaki Tsutsumi
- Applicant Address: JPX Tokyo
- Assignee: Mitsubishi Denki Kabushiki Kaisha
- Current Assignee: Mitsubishi Denki Kabushiki Kaisha
- Current Assignee Address: JPX Tokyo
- Priority: JPX7-314102 19951201
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/336 ; H01L21/8232 ; H01L21/8242 ; H01L23/485 ; H01L27/108 ; H01L23/48 ; H01L23/52 ; H01L29/40
Abstract:
An object is to provide a structure of a semiconductor device which allows higher degree of integration both in vertical and horizontal directions, and to provide manufacturing method therefor. The semiconductor device includes source.drain electrodes connected to n.sup.- and n.sup.+ source.drain regions of an MISFET and has a function as a part of a bit line, and a gate electrode connected to a first interconnection as a word line. Electrodes are insulated from each other by a sidewall insulating film, silicon oxide film or a silicon nitride film provided inbetween. Since the word line and the bit line do not cross in the same plane, the difference in level in the vertical direction can be reduced.
Public/Granted literature
- US5202156A Method of making an optical element mold with a hard carbon film Public/Granted day:1993-04-13
Information query
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