Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes first tiers located one over another, the first tiers including respective first memory cells and first control gates for the memory cells, the first memory cells located along respective first pillars, the first pillars extending through the first tiers; second tiers located one over another, the second tiers including respective second memory cells and second control gates for the memory cells, the second memory cells located along respective second pillars, the second pillars extending through the second tiers; and a dielectric structure formed in a slit between the first tiers and the second tiers, the dielectric structure including an edge along a length of the slit and adjacent the first tiers, wherein the edge has a repeating pattern of a shape.