- 专利标题: Low-Power Optical Input/Output Chiplet for Ethernet Switches (TeraPHYe)
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申请号: US17527483申请日: 2021-11-16
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公开(公告)号: US20220166533A1公开(公告)日: 2022-05-26
- 发明人: Vladimir Stojanovic , Hugo Saleh , Roy Edward Meade
- 申请人: Ayar Labs, Inc.
- 申请人地址: US CA Santa Clara
- 专利权人: Ayar Labs, Inc.
- 当前专利权人: Ayar Labs, Inc.
- 当前专利权人地址: US CA Santa Clara
- 主分类号: H04J14/02
- IPC分类号: H04J14/02 ; H04L12/931 ; H04Q11/00
摘要:
A network switch system-in-package includes a carrier substrate with a network switch chip and a plurality of photonic input/output modules disposed on the carrier substrate. Each of the plurality of photonic input/output modules includes a module substrate and a plurality of photonic chip pods disposed on the module substrate. Each photonic chip pod includes a pod substrate with a photonic input/output chiplet and a gearbox chiplet attached to the pod substrate. The photonic input/output chiplet includes a parallel electrical interface, a photonic interface, and a plurality of optical macros implemented between the photonic interface and the parallel electrical interface. The gearbox chiplet electrically connects with the parallel electrical interface of the photonic input/output chiplet and a serial electrical interface of the network switch chip. The gearbox chiplet converts between the parallel electrical interface of the photonic input/output chiplet and the serial electrical interface of the network switch chip.
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