Invention Application
US20100264482A1 MEMORY CELLS CONFIGURED TO ALLOW FOR ERASURE BY ENHANCED F-N TUNNELING OF HOLES FROM A CONTROL GATE TO A CHARGE TRAPPING MATERIAL
有权
通过增强的F-N隧道从控制门到电荷捕获材料的配置来允许用于擦除的记忆体
- Patent Title: MEMORY CELLS CONFIGURED TO ALLOW FOR ERASURE BY ENHANCED F-N TUNNELING OF HOLES FROM A CONTROL GATE TO A CHARGE TRAPPING MATERIAL
- Patent Title (中): 通过增强的F-N隧道从控制门到电荷捕获材料的配置来允许用于擦除的记忆体
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Application No.: US12829904Application Date: 2010-07-02
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Publication No.: US20100264482A1Publication Date: 2010-10-21
- Inventor: Arup Bhattacharyya , Kirk D. Prall , Luan C. Tran
- Applicant: Arup Bhattacharyya , Kirk D. Prall , Luan C. Tran
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Main IPC: H01L29/792
- IPC: H01L29/792
Abstract:
Memory cells including a control gate, a charge trapping material, and a charge blocking material between the control gate and the charge trapping material. The charge blocking material is configured to allow for erasure of the memory cell by enhanced F-N tunneling of holes from the control gate to the charge trapping material.
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Information query
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