The memory comprises, on a semi-conducting substrate, a matrix of cells arranged in lines and columns and each designed to store an information bit. Each cell of a column comprises a magnetic tunnel junction having a line terminal and a column terminal respectively connected to a line conductor and, by means of a transistor, to a first column conductor associated to said column and to a first adjacent column. A gate of the transistor is connected to a gate conductor. The column terminal of each tunnel junction of said column is connected, by means of an additional transistor, to a second column conductor associated to said column and to a second adjacent column. A gate of the additional transistor is connected to an additional gate conductor. The two transistors associated to a cell can have a common electrode.