A memory device includes a conductive segment, first and second rows of memory cells. The conductive segment receives a first reference voltage signal. The first row of memory cells is coupled to a first word line. The second row of memory cells is coupled to a second word line. The first row of memory cells includes first and second memory cells. The first memory cell is coupled to the conductive segment to receive the first reference voltage signal. The second row of memory cells includes third and fourth memory cells. The third memory cell is coupled to the conductive segment to receive the first reference voltage signal. The first and third memory cells share the conductive segment, and the third memory cell is arranged between the first and second memory cells. The second memory cell is arranged between the third and fourth memory cells.