- 专利标题: Handling non-correctable errors
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申请号: US17888590申请日: 2022-08-16
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公开(公告)号: US12019514B2公开(公告)日: 2024-06-25
- 发明人: David Matthew Thompson , Abhijeet Ashok Chachad
- 申请人: TEXAS INSTRUMENTS INCORPORATED
- 申请人地址: US TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: US TX Dallas
- 代理商 Michael T. Gabrik; Frank D. Cimino
- 主分类号: G06F11/10
- IPC分类号: G06F11/10 ; G06F9/30 ; G06F9/38 ; G06F9/448 ; G06F9/46 ; G06F9/48 ; G06F9/52 ; G06F12/0811 ; G06F12/0815 ; G06F12/0879 ; G06F12/0888 ; G06F12/0895 ; G06F12/128 ; G06F13/16 ; H03M13/15
摘要:
An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to receive a transaction from a master, the transaction directed to the first memory and comprising an address; re-calculate an error correcting code (ECC) for a line of data in the second memory associated with the address; determine that a non-correctable error is present in the line of data in the second memory based on a comparison of the re-calculated ECC and a stored ECC for the line of data; and in response to the determination that a non-correctable error is present in the line of data in the second memory, terminate the transaction without accessing the first memory.
公开/授权文献
- US20220391283A1 HANDLING NON-CORRECTABLE ERRORS 公开/授权日:2022-12-08
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