Invention Grant
- Patent Title: MRAM structure for balanced loading
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Application No.: US17884221Application Date: 2022-08-09
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Publication No.: US11937515B2Publication Date: 2024-03-19
- Inventor: Chih-Fan Huang , Hsiang-Ku Shen , Liang-Wei Wang , Chen-Chiu Huang , Dian-Hau Chen , Yen-Ming Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- The original application number of the division: US17002098 2020.08.25
- Main IPC: H10N50/80
- IPC: H10N50/80 ; H10B61/00 ; H10N50/01

Abstract:
Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.
Public/Granted literature
- US20220384712A1 MRAM STRUCTURE FOR BALANCED LOADING Public/Granted day:2022-12-01
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