Invention Grant
- Patent Title: Integrated circuit devices with well regions and methods for forming the same
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Application No.: US17345659Application Date: 2021-06-11
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Publication No.: US11735485B2Publication Date: 2023-08-22
- Inventor: Chi-Feng Huang , Chia-Chung Chen , Victor Chiang Liang , Mingo Liu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- The original application number of the division: US13539027 2012.06.29
- Main IPC: H01L27/098
- IPC: H01L27/098 ; H01L21/8249 ; H01L27/06 ; H01L27/085 ; H01L29/732 ; H01L29/808 ; H01L29/861 ; H01L29/93 ; H01L27/07 ; H01L29/06

Abstract:
A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.
Public/Granted literature
- US20210305099A1 Integrated Circuit Devices with Well Regions and Methods for Forming the Same Public/Granted day:2021-09-30
Information query
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