Invention Grant
- Patent Title: Method for forming chip package structure
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Application No.: US17373016Application Date: 2021-07-12
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Publication No.: US11600575B2Publication Date: 2023-03-07
- Inventor: Shin-Puu Jeng , Techi Wong , Po-Yao Lin , Ming-Chih Yew , Po-Hao Tsai , Po-Yao Chuang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/00 ; H01L21/48 ; H01L25/00 ; H01L21/683 ; H01L25/10 ; H01L23/31 ; H01L21/768

Abstract:
A method for forming a chip package structure is provided. The method includes forming a conductive pad over a carrier substrate. The method includes forming a substrate layer over the carrier substrate, wherein the conductive pad is embedded in the substrate layer, and the substrate layer includes fibers. The method includes forming a through hole in the substrate layer and exposing the conductive pad. The method includes forming a conductive pillar in the through hole. The method includes forming a recess in the substrate layer. The method includes disposing a chip in the recess. The method includes forming a molding layer in the recess. The method includes forming a redistribution structure over the substrate layer, the conductive pillar, the molding layer, and the chip. The method includes removing the carrier substrate.
Public/Granted literature
- US20210343652A1 METHOD FOR FORMING CHIP PACKAGE STRUCTURE Public/Granted day:2021-11-04
Information query
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