发明授权
- 专利标题: Enhancement-depletion cascode arrangements for enhancement mode III-N transistors
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申请号: US16419240申请日: 2019-05-22
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公开(公告)号: US11527532B2公开(公告)日: 2022-12-13
- 发明人: Nidhi Nidhi , Han Wui Then , Marko Radosavljevic , Sansaptak Dasgupta , Paul B. Fischer , Rahul Ramaswamy , Walid M. Hafez , Johann Christian Rode
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Akona IP PC
- 主分类号: H01L29/66
- IPC分类号: H01L29/66 ; H01L27/088 ; H01L29/20 ; H01L29/205 ; H01L29/40 ; H01L23/31 ; H01L23/00 ; H01L29/778 ; H01L25/065
摘要:
Disclosed herein are IC structures, packages, and devices that include III-N transistor-based cascode arrangements that may simultaneously realize enhancement mode transistor operation and high voltage capability. In one aspect, an IC structure includes a source region, a drain region, an enhancement mode III-N transistor, and a depletion mode III-N transistor, where each of the transistors includes a first and a second source or drain (S/D) terminals. The transistors are arranged in a cascode arrangement in that the first S/D terminal of the enhancement mode III-N transistor is coupled to the source region, the second S/D terminal of the enhancement mode III-N transistor is coupled to the first S/D terminal of the depletion mode III-N transistor, and the second S/D terminal of the depletion mode III-N transistor is coupled to the drain region.
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