- 专利标题: Self-aligned contacts for 3D logic and memory
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申请号: US16721583申请日: 2019-12-19
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公开(公告)号: US11335599B2公开(公告)日: 2022-05-17
- 发明人: Lars Liebmann , Jeffrey Smith , Anton J. deVilliers , Kandabara Tapily
- 申请人: Tokyo Electron Limited
- 申请人地址: JP Tokyo
- 专利权人: Tokyo Electron Limited
- 当前专利权人: Tokyo Electron Limited
- 当前专利权人地址: JP Tokyo
- 代理机构: Oblon, McClelland, Maier & Neustadt, L.L.P.
- 主分类号: H01L21/768
- IPC分类号: H01L21/768 ; H01L23/522 ; H01L27/118 ; H01L21/8238 ; H01L21/822 ; H01L27/11
摘要:
A semiconductor device includes dielectric layers and local interconnects that are stacked over a substrate alternatively, and extend along a top surface of the substrate laterally. Sidewalls of the dielectric layers and sidewalls of the local interconnects have a staircase configuration. The local interconnects are spaced apart from each other by dielectric layers and have uncovered portions by the dielectric layers. The semiconductor device also includes conductive layers selectively positioned over the uncovered portions of the local interconnects, where sidewalls of the conductive layers and sidewalls of the local interconnects are coplanar. The semiconductor device further includes isolation caps that extend from the dielectric layers. The isolation caps are positioned along sidewalls of the conductive layers and sidewalls of the local interconnects so as to separate the conductive layers from one another.
公开/授权文献
- US20200373203A1 SELF-ALIGNED CONTACTS FOR 3D LOGIC AND MEMORY 公开/授权日:2020-11-26
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