- 专利标题： Gated bipolar junction transistors, memory arrays, and methods of forming gated bipolar junction transistors
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申请号： US16436689申请日： 2019-06-10
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公开(公告)号： US10886273B2公开(公告)日： 2021-01-05
- 发明人: Rajesh N. Gupta , Farid Nemati , Scott T. Robins
- 申请人： Micron Technology, Inc.
- 申请人地址： US ID Boise
- 专利权人： Micron Technology, Inc.
- 当前专利权人： Micron Technology, Inc.
- 当前专利权人地址： US ID Boise
- 代理机构： Wells St. John P.S.
- 主分类号： H01L21/8249
- IPC分类号： H01L21/8249 ; H01L27/102 ; H01L29/735 ; H01L29/73 ; H01L21/02 ; H01L21/8229 ; H01L29/16 ; H01L29/732 ; H01L29/739 ; H01L27/108 ; H01L29/78
摘要：
Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
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