A semiconductor device includes a column operation control circuit and a bank column address generation circuit. The column operation control circuit generates first and second bank address control signals as well as first and second bank control pulses from first and second bank selection signals in response to a synthesis control pulse such that data in a first bank and data in a second bank are simultaneously outputted in a first mode. The bank column address generation circuit generates first and second bank column addresses for selecting the first and second banks from a column address in response to the first and second bank address control signals.