- 专利标题: Apparatuses and methods including two transistor-one capacitor memory and for accessing same
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申请号: US16105631申请日: 2018-08-20
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公开(公告)号: US10854276B2公开(公告)日: 2020-12-01
- 发明人: Christopher J. Kawamura , Scott J. Derner
- 申请人: MICRON TECHNOLOGY, INC.
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 代理机构: Dorsey & Whitney LLP
- 主分类号: G11C11/24
- IPC分类号: G11C11/24 ; G11C11/4091 ; G11C7/06 ; G11C11/403 ; G11C11/4094 ; G11C11/4097 ; H01L27/108 ; G11C5/02 ; G11C7/18 ; G11C8/16 ; G11C11/4096
摘要:
Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.
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