Invention Grant
- Patent Title: Semiconductor structure and method for forming the same
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Application No.: US16390828Application Date: 2019-04-22
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Publication No.: US10658252B2Publication Date: 2020-05-19
- Inventor: Jia-Ming Lin , Wei-Ken Lin , Shiu-Ko JangJian , Chun-Che Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L21/311 ; H01L21/8234 ; H01L21/84 ; H01L21/3115 ; H01L21/762 ; H01L29/78

Abstract:
A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.
Public/Granted literature
- US20190252273A1 Semiconductor Structure and Method for Forming the Same Public/Granted day:2019-08-15
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