Invention Grant
- Patent Title: Bit tagging method, memory control circuit unit and memory storage device
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Application No.: US15890326Application Date: 2018-02-06
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Publication No.: US10522234B2Publication Date: 2019-12-31
- Inventor: Wei Lin , Yu-Hsiang Lin , Yu-Cheng Hsu
- Applicant: PHISON ELECTRONICS CORP.
- Applicant Address: TW Miaoli
- Assignee: PHISON ELECTRONICS CORP.
- Current Assignee: PHISON ELECTRONICS CORP.
- Current Assignee Address: TW Miaoli
- Agency: JCIPRNET
- Priority: TW106144129A 20171215
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C16/34 ; G06F11/10 ; G11C16/10 ; G11C29/52 ; G11C16/26

Abstract:
A bit tagging method, a memory control circuit unit and a memory storage device are provided. The method includes: reading first memory cells according to a first reading voltage to generate a first codeword and determining whether the first codeword is a valid codeword, and the first codeword includes X bits; if not, reading the first memory cells according to a second reading voltage to generate a second codeword and determining whether the second codeword is the valid codeword, and the second codeword includes X bits; and if the second codeword is not the valid codeword and a Yth bit in the X bits of the first codeword is different from a Yth bit in the X bits of the second codeword, recording the Yth bit in the X bits as an unreliable bit, and Y is a positive integer less than or equal to X.
Public/Granted literature
- US20190189228A1 BIT TAGGING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE Public/Granted day:2019-06-20
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