- 专利标题: Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processor
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申请号: US15103765申请日: 2013-12-23
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公开(公告)号: US10133582B2公开(公告)日: 2018-11-20
- 发明人: Nikolay Kosarev , Sergey Y. Shishlov , Jayesh Iyer , Alexander V. Butuzov , Boris A. Babayan , Andrey Kluchnikov
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Alliance IP, LLC
- 国际申请: PCT/IB2013/003083 WO 20131223
- 国际公布: WO2015/097494 WO 20150702
- 主分类号: G06F9/38
- IPC分类号: G06F9/38 ; G06F9/30
摘要:
A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and each strand ordered by program order (PO). The processor also includes a second logic to determine an oldest undispatched instruction in the instruction stream and store an associated PO value of the oldest undispatched instruction as an executed instruction pointer. The instruction stream includes dispatched and undispatched instructions. The processor also includes a third logic to determine a most recently retired instruction in the instruction stream and store an associated PO value of the most recently retired instruction as a retirement pointer, a fourth logic to select a range of instructions between the retirement pointer and the executed instruction pointer, and a fifth logic to identify the range of instructions as eligible for retirement.
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