Invention Grant
- Patent Title: Mixed redundancy scheme for inter-die interconnects in a multichip package
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Application No.: US14737246Application Date: 2015-06-11
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Publication No.: US10082541B2Publication Date: 2018-09-25
- Inventor: Dana How , Dinesh Patil , Arifur Rahman , Jeffrey Erik Schulz
- Applicant: Altera Corporation
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Treyz Law Group, P.C.
- Agent Jason Tsai; Vineet Dixit
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F13/20 ; G06F3/00 ; G01R31/3185 ; G01R31/28 ; H01L25/065 ; G06F11/16 ; G06F11/18 ; G06F11/20 ; G06F11/00

Abstract:
Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.
Public/Granted literature
- US10031182B2 Mixed redundancy scheme for inter-die interconnects in a multichip package Public/Granted day:2018-07-24
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