- 专利标题： CMOS nanowire structure
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申请号： US15411095申请日： 2017-01-20
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公开(公告)号： US10074573B2公开(公告)日： 2018-09-11
- 发明人: Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Annalisa Cappellani , Stephen M. Cea , Rafael Rios , Glenn A. Glass
- 申请人： Intel Corporation
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Schwabe, Williamson & Wyatt, P.C.
- 主分类号： H01L21/8238
- IPC分类号： H01L21/8238 ; H01L27/092 ; H01L27/12 ; H01L29/06 ; B82Y10/00 ; H01L29/66 ; H01L29/775 ; H01L21/84 ; H01L29/423 ; H01L29/10 ; H01L29/78
摘要：
Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.
公开/授权文献
- US20170133277A1 CMOS NANOWIRE STRUCTURE 公开/授权日：2017-05-11
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