The present invention discloses semiconductor chip. It features including plurality of integrated circuit chip area surrounded by cut line, cutting integrated circuit chip, each chip having four corners, protective layer simultaneously covering aforementioned integrated circuit chip area and cut line, first groove being etched penetrating aforementioned protective layer, then at least etching to dielectric layer and only arranged four corner of integrated circuit chip, second groove etching penetrating aforementioned protective layer configured on position near by aforementioned first groove, and protecting seal ring structure located between integrated circuit chip and first groove.