A line layout structure and layout method as well as a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line, a local word line, a global bit line, and a local bit line, all these lines are individually disposed at conductive layers among at least three layers, with at least two of them are together disposed in parallelon one conductive layer. Signal lines constituting a semiconductor memory device are disposed in a hierarchical structure, whereby a semiconductor memory device advantageously having high integration, high speed and high performance may be obtained.