The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and adrain region. Source and drain regions of a p channel type MOS transistor are formed in an n^- type semiconductor layer in an SOI substrate. In addition, an n type impurity region is formedin the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly belowan upper surface of the semiconductor layer between the source region and the drain region.