Techniques are provided for applying clock signals to a pipelined, reduced instruction set computing (RISC) processor used within a mobile subscriber station such as a cellular telephone. Specific techniques described herein are provided for powering down the RISC processor while providing synchronization between the processor and peripheral components by ensuring completion of current pipline stages of the processor prior to power down. Other specific techniques are directed to switching between synchronous or asynchronous clock signals while avoiding clocking glitches that might cause unpredictable behavior within the RISC processor. Method and apparatus embodiments of the techniques are described.