The invention relates to the technical field of integrated circuit testing, particularly to a test structure and a method for monitoring probe mark offset by using the same. According to the test structure disclosed by the invention, a novel test structure is introduced to conventional WAT (wafer acceptance test); the number N (N is greater than or equal to 4) of metal bond pads is consistent to the number of monitored probe clamping pins; an active device is put below each metal bond pad; gates, sources and drains of the N (N is greater than or equal to 4) active devices, and a substrate are connected in parallel to be connected to four different bond pads respectively; and by measuring saturation current of the active devices in different positions below the bond pads, the offset condition of the probe pins can be monitored in real time.