A method for manufacturing an integrated circuit is provided. The method includes forming first and second semiconductor fins; forming first and second dielectric fin sidewall structures on opposite sidewalls of the first semiconductor fin, wherein the first dielectric fin sidewall structure is higher than the second dielectric fin sidewall structure, and the second dielectric fin sidewall structure is between the first and second semiconductor fins; recessing at least a portion of the first semiconductor fin between the first and second dielectric fin sidewall structures until a top of the recessed portion of the first semiconductor fin is lower than a top of the first dielectric fin sidewall structure; and forming a first epitaxy structure on the recessed portion of the first semiconductor fin.