The invention provides a wafer-level chip package backside interconnection structure and a manufacturing method thereof and belongs to the field of semiconductor packaging. The packaging method comprises the steps of 1, providing a wafer with a functional region, a bonding pad and a dielectric layer; 2, providing a cover plate, and bonding the cover plate with the wafer together by means of the bonding glue; 3, conducting the silicon etching operation on the lower surface of the substrate of the wafer, and removing the silicon material in scribe lines on the lower surface of the substrate of the wafer and the silicon material on the bonding pad to form a first groove body and a second groove body; 4, manufacturing a redistribution layer on the lower surface of the substrate of the wafer; 5, cutting the wafer along the scribe lines to form the package of the single chip. According to the technical scheme of the invention, the challenge of multiple materials on the cutting process is reduced, and the yield of the cutting process is improved. Meanwhile, the packaging reliability is improved. Moreover, the stress applied onto the periphery of the bonding pad is released, so that the stress generated due to the thermal mismatch of different materials is reduced. Therefore, the stratifying, cracking and other invalid phenomena at the interfaces of different materials are alleviated.