A shift register is configured by connecting unit circuits (1) in a multitude of stages. An output transistor (Tr1) switches between whether or not to output a clock signal (CKA) in accordance with the gate potential. The drain terminal of an initialization transistor (Tra) is connected to the gate terminal of said Tr1, and the source terminal is connected to an output terminal (OUT) or a clock terminal (CKA). At the time of outputting a clock signal that initially has a low-level potential and that also has a high-level potential, the source terminal of said Tra is connected to a nodal point having a potential at the same level as that of the clock signal. Thus, at the time of outputting a clock signal having a high-level potential, the application of high voltage between the source and the drain of said Tra is prevented, and the degradation/breakdown of the initialization transistor is prevented.