According to the present invention, a memory array (10) is provided with: a resistance change-type memory cell array (11) that is configured by connecting a first cell transistor and a resistance change element in series; and a reference cell array (12) that is configured by connecting a second cell transistor and a resistance element in series; the second cell transistor of the reference cell array (12) being connected to a reference source line (RSL) and the resistance element being connected to a reference bit line (RBL), a dummy memory cell inside the memory cell array (11) being connected to the reference bit line (RBL), and both ends of the resistance change element of the dummy memory cell being short-circuited by the reference bit line (RBL).