In this invention, high manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS.SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. The threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is respectively programmed into control memories according to the results of determination. The levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS.SRAM are controlled to a predetermined error span. A body bias voltage corresponding to a reverse body bias or anextremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.