US11264848B2
A rotor core has first and second magnet insertion holes along an outer circumference, and first and second slits along an inner circumference. The first and second slits have first and second facing portions facing each other. The first facing portion has a first inner end and a first outer end. The second facing portion has a second inner end and a second outer end. An inter-slit portion is provided between the first and second facing portions and is defined by a first straight line connecting the first and second inner ends and a second straight line connecting the first and second outer ends. In a radial direction of the rotor core, a minimum distance D1 from the inner circumference to the slits, a minimum width W1 of the slits, and a length W2 of the inter-slit portion satisfy at least one of D1
US11264847B2
A reluctance motor is used in a compressor. The reluctance motor includes a rotor having a rotor core that has an annular outer circumference about an axis, having a plurality of magnetic poles along the outer circumference, and having no permanent magnet, and a stator including a stator core that surrounds the rotor from an outer side in a radial direction about the axis and a winding wound around the stator core in wave winding. Each of the plurality of magnetic poles has a first slit formed in the rotor core and a second slit formed on an inner side of the first slit in the radial direction. The stator core has a refrigerant passage through which refrigerant passes in a direction of the axis.
US11264841B2
The wireless power transmission is a system for providing wireless charging and/or primary power to electronic/electrical devices via microwave energy. The microwave energy is focused to a location by a power transmitter having one or more adaptively-phased microwave array emitters. Rectennas within the device to be charged receive and rectify the microwave energy and use it for battery charging and/or for primary power.
US11264838B2
A semiconductor device formed in a single semiconductor integrated circuit, the semiconductor device including: a transmission signal circuit block; a reception signal circuit block; a signal processing circuit block; and at least one of a charging control circuit block or a monitoring circuit block.
US11264830B2
A light-emitting diode (LED) luminaire comprises an emergency-operated portion comprising a rechargeable battery with a terminal voltage, a self-diagnostic circuit, and a node modulator-demodulator (MODEM). The LED luminaire can auto-switch from a normal power to an emergency power according to availability of the normal power and whether a rechargeable battery test is initiated. The self-diagnostic circuit comprises a clock and is configured to initiate self-diagnostic tests and to auto-evaluate battery performance according to test schedules with the terminal voltage examined and test results stored. The LED luminaire further comprises a remote controller configured to initiate control signals with phase-shift keying (PSK) signals transmitted and to collect test data to and from the node MODEM. The node MODEM is configured to demodulate the PSK signals and to send commands to the self-diagnostic circuit to request responses accordingly.
US11264826B2
The present invention provides an energy storage management device, a power generation system and a power distribution method based on blockchain technology, which comprises an energy storage battery pack, a plurality of battery pack arrays, and an energy storage battery pack connected with a load; AC/DC bidirectional inverter module is connected with power generation device, energy storage battery pack and load respectively; the control module is electrically connected with the energy storage battery pack and AC/DC two-way inverter module respectively. It is used to control the AC/DC two-way inverter module that converts the output electric energy of the generation device and transfer the energy storage battery pack. Furthermore, it is used to control the AC/DC two-way inverter module and the energy storage battery pack to transmit electric energy to the load.
US11264823B2
A wireless charger includes multiple transmitter coils, first and second drivers, and a controller. The transmitter coils are arranged close to and/or overlap with each other. The first driver is coupled with at least one of the transmitter coils to drive the transmitter coil to communicate with and/or provide power over a first channel to receiver devices. The second driver is coupled with at least another one of the transmitter coils to drive the transmitter coil to communicate with and/or provide power over a second channel to receiver devices. The controller is coupled with the first and second drivers and enables only one of the first and second drivers at a time during a first stage.
US11264820B2
A facility server manages battery charge of a plurality of robots in an environment where a charging device is shared by the plurality of robots. A waiting information acquisition unit acquires waiting information related to whether there is a robot which cannot use the charging device and is waiting, because another robot is charging a battery using the charging device. A charge suspension control unit controls, when there is a robot which cannot use the charging device and is waiting, control the other robot to suspend charging a battery.
US11264818B2
A charger adapted to charge either one of a first battery pack and a second battery pack. The first battery pack and the second battery pack have respectively a first interface and a second interface being substantially different from each other. The charger includes a housing having a receiving area in which the first battery pack and the second battery pack can be selectively received in such a way that the first battery pack is accommodated in a first region and the second battery pack is accommodated in a second region. The receiving area is at least partially defined by the first region partially overlapping the second region. The charger according to the invention is adapted to charge more than one type of battery pack, which saves cost and space needed for two separate chargers.
US11264814B2
Battery circuitry forms part of apparatus for connecting a battery power source to a portable electronic device. The battery circuitry is configured to detect a transitioning of an enable signal, caused by actuation of a power switch, from a de-asserted state to an asserted state. In response to detecting the transitioning of the enable signal, the battery circuitry is further configured to open an electrical path within the battery circuitry. The path, when opened, connects the battery power source in a manner that permits powering on of the portable electronic device.
US11264810B2
Systems and methods are provided for balancing battery modules following fast charging, particularly with respect to fast charging lithium ion batteries with metalloid-based anodes. Charge balancing among multiple battery modules connected in series may be carried out by short-circuiting fully charged modules while adjusting the voltage and/or current level supplied by a charger, to fully charge remaining modules. A balancing module comprising a controller and switching circuitry may be configured to implement the charge balancing in association with the charger and its battery management system, and monitoring the battery modules. Advantageously, disclosed switching balancing is more efficient than prior art passive balancing and simpler in implementation than prior art active balancing.
US11264802B2
A method for controlling a renewable energy power plant comprising a plurality of renewable energy generators, the method comprising: carrying out the following steps dynamically: determining a reactive power capability value of the power plant based on the generated active power of each of the renewable energy generators within the power plant; determining a reactive power exchange limit value based on a measured grid voltage level; and controlling the power plant so that the generated reactive power does not exceed the lower of the determined reactive power capability value and the determined reactive power exchange limit value that are determined dynamically.
US11264792B2
A secondary battery protection circuit for protecting a secondary battery, including: a low-voltage detecting circuit configured to detect a voltage across the secondary battery that is lower than a second voltage for low voltage detection, the second voltage being set to be lower than a first voltage for overdischarge detection; and a switching circuit configured to cause a gate of a charge control NMOS transistor to be fixed at a potential at a high side power supply terminal, upon detecting, by the low-voltage detecting circuit, that the voltage across the secondary battery is lower than the second voltage for low voltage detection.
US11264787B2
Implementations include a compartmentalized plug-in load center having connector receptacles for load circuit wiring connection to the load center and a plug-in back plate to connect the plug-in load center to a vertical power busway within a utility wall panel of a building, and a method for installing the load center in a building with a vertical power busway.
US11264775B2
Disclosed is a system and method for remote sensing, surface profiling, object identification, and aiming based on two-photon population inversion and subsequent photon backscattering enhanced by superradiance using two co-propagating pump waves. The present disclosure enables efficient and highly-directional photon backscattering by generating the pump waves in properly pulsed time-frequency modes, proper spatial modes, with proper group-velocity difference in air. The pump waves are relatively delayed in a tunable pulse delay device and launched to free space along a desirable direction using a laser-pointing device. When the pump waves overlap in air, signal photons will be created through two-photon driven superradiant backscattering if target gas molecules are present. The backscattered signal photons propagate back, picked using optical filters, and detected. By scanning the relative delay and the launching direction while the signal photons are detected, three-dimensional information of target objects is acquired remotely.
US11264753B2
A connector includes a pair of outer conductors including a first outer conductor and a second outer conductor assembled together and slidable with respect to each other, a pair of center conductors arranged within the outer conductors, an insulation seat, and an elastic element. The center conductors include a first center conductor and a second center conductor assembled together and slidable with respect to each other. The first outer conductor and the first center conductor are fixed to the insulation seat. A first end of the elastic element abuts against the first outer conductor or the insulation seat. The first outer conductor and the first center conductor are both in electrical contact with a first electrical component under a pressing force from the elastic element.
US11264745B2
An electrical connector includes an insulative housing with a plurality of passageways extending through opposite upper and lower surfaces thereof, and a plurality of contacts retained in the corresponding passageways, respectively. The contact includes a main body, a spring arm extending from an upper end of the main body with a contacting section at a free end region thereof, and a tab extending upwardly from the main body for assembling the contact into the corresponding passageway. An auxiliary part extends from a side edge of the main body at an angle with a solder pad at the bottom end for securing a solder ball thereto. The tab is dimensioned to allow a fixture to grasp thereon for applying a downward force thereto during downwardly inserting the contact into the passageway, and is optionally adapted to be removed when the contact is moved to almost the final position.
US11264732B2
An antenna module includes a dielectric substrate, multiple patch antennas provided at a first main surface side of the dielectric substrate, and an RFIC mounted at a second main surface side of the dielectric substrate. The multiple patch antennas include multiple sets of antenna groups each composed of the multiple patch antennas periodically arranged at a pitch Px in the X-axis direction, which is one of a polarization direction and a direction perpendicular to the polarization direction. The multiple sets of antenna groups are periodically arranged at a pitch Py in the Y-axis direction, which is the other of the polarization direction and the direction perpendicular to the polarization direction, and each of the multiple sets of antenna groups is arranged so as to be shifted from another antenna group adjacent in the second direction by an offset distance Dx in the first direction.
US11264714B2
A method and apparatus for beamforming in a wireless communication system are provided. The method of supporting beamforming in a wireless communication device includes detecting a direction change of the wireless communication device while communicating with a peer device. The method of supporting beamforming in a wireless communication device also includes adjusting a beam direction for communication with the peer device based on information indicating a direction change of the wireless communication device.
US11264712B2
A radar sensor module includes a substrate, at least one transmit antenna formed on a surface of the substrate, and at least one receive antenna formed on the surface of the substrate. A radome is disposed over the surface of the substrate and the at least one transmit antenna and the at least one receive antenna, such that a gap is located between the surface of the substrate and an underside of the radome in which a portion of radiation emitted from the at least one transmit antenna can propagate. At least one trench is formed in the underside of the radome and is electromagnetically coupled to the gap, the at least one trench being sized, shaped and positioned with respect to the gap such that the portion of radiation emitted from the at least one transmit antenna is substantially prevented from propagating toward the receiving antenna.
US11264698B2
A passive radiofrequency transponder comprises a radiating dipole antenna consisting of a single-strand helical spring having an axis, a median plane, a pitch and a diameter for a given wire diameter, and an electronic portion located inside the radiating antenna. The electronic portion comprises an electronic chip electrically connected to a primary antenna that is electromagnetically coupled to the radiating antenna. The primary antenna has an axis parallel to the axis of the radiating antenna and a median plane superposed with the median plane of the radiating antenna. The primary antenna is circumscribed by a cylinder the diameter of which is larger than one third of the inside diameter of the radiating antenna. The radiofrequency transponder is characterized in that, in a first region of the radiating antenna, in which the latter is not located plumb with the electronic portion, the first helix pitch of the radiating antenna is larger than the second helix pitch of the radiating antenna that does not form part of this first region.
US11264697B2
The present disclosure provides a linked antenna pair for a shipping container having a thermally insulated and electromagnetically shielded cavity for holding a payload. The linked antenna pair comprises a first antenna disposed inside the cavity, a second antenna disposed outside the cavity, and a feed line that electrically connects the first antenna to the second antenna.
US11264687B2
Microelectronic assemblies that include a lithographically-defined substrate integrated waveguide (SIW) component, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate portion having a first face and an opposing second face; and an SIW component that may include a first conductive layer on the first face of the package substrate portion, a dielectric layer on the first conductive layer, a second conductive layer on the dielectric layer, and a first conductive sidewall and an opposing second conductive sidewall in the dielectric layer, wherein the first and second conductive sidewalls are continuous structures.
US11264686B2
This disclosure describes a dielectric filter and a communications device. In one example, the dielectric filter includes at least two dielectric resonators, a first through-hole is disposed between at least one pair of adjacent dielectric resonators, and the first through-hole is configured to cut a magnetic field between the at least one pair of adjacent dielectric resonators. In some implementations, a magnetic field distribution in the dielectric filter may be cut via the first through-hole, so that a magnetic field distribution area is reduced, and a high-order harmonic wave frequency can be increased, thereby improving a remote suppression capability and meeting the specification requirements.
US11264685B2
The present disclosure relates to a linkage mechanism for a phase shifter assembly, comprising a rotation device having a rotation shaft fixed to a substrate of the phase shifter assembly and a rotation member configured to rotate about said rotation shaft; a first drive member which can be operatively engaged to the rotation member such that rotation of the rotation member can cause movement of the first drive member; a second drive member disposed on and moving together with the rotation member; and a translation device including a translation member which can be operatively engaged to the second drive member such that movement of the second drive member can cause movement of the translation member, wherein the rotation device and the translation device are configured to move in association with each other during operation of the phase shifter assembly. The present disclosure also relates to a phase shifter assembly including the above-mentioned linkage mechanism.
US11264676B2
Provided are separators for use in an electrochemical cell comprising (a) an inorganic oxide and (b) an organic polymer, wherein the inorganic oxide comprises organic substituents. Also provided are electrochemical cells comprising such separators.
US11264645B2
A lithium battery includes a cathode including a cathode active material, an anode including an anode active material, and an organic electrolytic solution between the cathode and the anode. The anode active material includes a metal-based anode active material. The organic electrolytic solution includes a first lithium salt; an organic solvent; and a bicyclic sulfate-based compound represented by Formula 1 below: wherein, in Formula 1, each of A1, A2, A3, and A4 is independently a covalent bond, a substituted or unsubstituted C1-C5 alkylene group, a carbonyl group, or a sulfinyl group, wherein both A1 and A2 are not a covalent bond and both A3 and A4 are not a covalent bond.
US11264640B2
A garnet-type ion-conducting oxide configured to inhibit lithium carbonate formation on the surface of crystal particles thereof, and a method for producing an oxide electrolyte sintered body using the garnet-type ion-conducting oxide. The garnet-type ion-conducting oxide represented by a general formula (Lix-3y-z, Ey, Hz)LαMβOγ (where E is at least one kind of element selected from the group consisting of Al, Ga, Fe and Si; L is at least one kind of element selected from an alkaline-earth metal and a lanthanoid element: M is at least one kind of element selected from a transition element which be six-coordinated with oxygen and typical elements in groups 12 to 15 of the periodic table; 3≤x−3y−z≤; 0≤y≤0.22; C≤z≤2.8; 2.5≤α≤3.5; 1.5≤≈≤2.5; and 11≤γ≤13), wherein a half-width of a diffraction peak which has a highest intensity and which is observed at a diffraction angle (2θ) in a range of from 29° to 32° as a result of X-ray diffraction measurement using CuKα radiation, is 0.164° or less.
US11264637B2
One variation of a battery unit includes: a substrate including silicon and defining a cell, wherein the cell includes a base encompassed by a continuous wall and a set of posts extending normal to the base; an electrolyte material coating vertical surfaces of each post, in the set of posts, and vertical surfaces of the continuous wall in the cell; a cathode material filling the cell over the electrolyte material, between posts in the set of posts, and between the set of posts and the continuous wall; a seal extending along a top of the continuous wall; and a cathode current collector bonded to the seal, electrically coupled to the cathode material, and cooperating with the substrate to enclose the cell to form a single-cell battery.
US11264635B2
A secondary battery includes a positive electrode having a positive electrode current collector and a positive electrode active material layer; a negative electrode having a negative electrode current collector and a negative electrode active material layer; a separator interposed between the electrodes; a electrolyte; a positive electrode lead; and an insulating tape that covers part of the positive electrode. The positive electrode current collector has an exposed portion connected to the positive electrode lead. The positive electrode lead has an extending portion that projects from the exposed portion and an overlapping portion that overlaps the exposed portion. At least part of the exposed portion and at least part of the overlapping portion are covered with the insulating tape. The insulating tape has a substrate layer and an adhesive layer. The substrate layer contains a polyimide. The adhesive layer has an electrical resistance of 1 kΩ/mm2 or more at 500° C.
US11264629B2
A method for manufacturing a membrane-electrode assembly (MEA) is provided. In particular, first and second sub-gasket sheets are continuously supplied and an electrode membrane sheet having gaps formed therein so that the amount of an electrolyte membrane used is reduced is discontinuously supplied. Thus, the minimum length of the electrolyte membrane protrudes between sub-gaskets and the electrolyte membrane together with electrode catalyst layers is bonded to the sub-gaskets
US11264628B2
The present invention provides a relative humidity and condensed water estimator for a fuel cell and a method for controlling condensed water drain using the same. Here, the relative humidity and condensed water estimator is utilized in control of the fuel cell system involving control of anode condensed water drain by outputting at least two of signals comprising air-side relative humidity, hydrogen-side relative humidity, air-side instantaneous or cumulative condensed water, hydrogen-side instantaneous or cumulative condensed water, instantaneous and cumulative condensed water of the humidifier, membrane water contents, catalyst layer oxygen partial pressure, catalyst layer hydrogen partial pressure, stack or cell voltage, air-side catalyst layer relative humidity, hydrogen-side catalyst layer relative humidity, oxygen supercharging ratio, hydrogen supercharging ratio, residual water in a stack, and residual water in a humidifier.
US11264625B2
A cooling plate assembly includes an anode half-plate having an anode upper surface and an opposing anode lower surface, and a cathode half-plate having a cathode upper surface and an opposing cathode lower surface, the cathode lower surface configured to engage the anode upper surface. The assembly further includes a cooling tube disposed between and engaging the anode upper surface and the cathode lower surface.
US11264624B2
An electrocatalyst material having improved stability to corrosion compared to existing conductive high surface area carbon and metal carbide support materials is disclosed. The electrocatalyst material comprises (i) metal carbide nanotubes and (ii) a metal or metal alloy deposited on the metal carbide nanotubes. The electrocatalyst material is suitable for oxidising hydrogen, reducing oxygen or evolving hydrogen.
US11264622B2
A method for manufacturing a membrane-electrode assembly for a fuel cell comprises the following steps: a first step during which a chemical catalyst element is deposited on a first face of an ion-exchanging membrane, the membrane being held on a support film; a second step during which the membrane is unglued from the support film; a third step during which the membrane is inserted between two reinforcing elements; and a fourth step during which a chemical catalyst element is deposited on the part left free of the second face of the membrane.
US11264611B2
This application relates to a battery comprising a positive electrode plate, a separator, and a negative electrode plate, wherein the positive electrode plate comprises a positive electrode current collector and at least two layers of positive active material coated on at least one surface of the positive electrode current collector, and wherein an underlying positive active material layer in contact with the positive electrode current collector comprises a first positive active material, a first polymer material and a first conductive material; and wherein an upper positive active material layer in contact with the underlying positive active material layer and away from the positive electrode current collector comprises a second positive active material, a second polymer material and a second conductive material, and the first polymer material comprises fluorinated polyolefin and/or chlorinated polyolefin polymer material. The battery has good safety and improved electrical properties.
US11264610B2
This application relates to a battery comprising a positive electrode plate, a separator, and a negative electrode plate, wherein the positive electrode plate comprises a positive electrode current collector and at least two layers of positive active material coated on at least one surface of the positive electrode current collector, and wherein the underlying positive active material layer in contact with the positive electrode current collector comprises a first positive active material, a first polymer material and a first conductive material, and the first polymer material comprises fluorinated polyolefin and/or chlorinated polyolefin polymer material. The battery has good safety and improved electrical properties.
US11264607B2
An alkaline electrochemical cell includes a cathode, an anode which includes an anode active material, and a non-conductive separator disposed between the cathode and the anode, wherein from about 20% to about 50% by weight of the anode active material relative to a total amount of anode active material has a particle size of less than about 75 μm, and wherein the separator includes a unitary, cylindrical configuration having an open end, a side wall, and integrally formed closed end disposed distally to the open end.
US11264606B2
Methods of pretreating an electroactive material comprising lithium titanate oxide (LTO) include contacting a surface of the electroactive material with a pretreatment composition. In one variation, the pretreatment composition includes a salt of lithium fluoride salt selected from the group consisting of: lithium hexafluorophosphate (LiPF6), lithium tetrafluoroborate (LiBF4), and combinations thereof, and a solvent. In another variation, the pretreatment composition includes an organophosphorus compound. In this manner, a protective surface coating forms on the surface of the electroactive material. The protective surface coating comprises fluorine, oxygen, phosphorus or boron, as well as optional elements such as carbon, hydrogen, and listed metals, and combinations thereof.
US11264604B2
A negative electrode material includes at least a graphite particle and a first metal oxide. The graphite particle includes at least one open pore. The graphite particle has a porosity not lower than 13% and not higher than 66%. The first metal oxide adheres to an inner wall of the open pore. The first metal oxide is lithium ion conductive and electron conductive. The first metal oxide is not smaller than 0.5 part by mass and not greater than 20 parts by mass with respect to 100 parts by mass of graphite particle.
US11264598B2
A battery having a cathode and a composite anode is provided. In one embodiment, the composite anode may include a lithium metal anode, a solid electrolyte and at least one interface layer. The interface layer improves the uniformity of the surface of the solid electrolyte thereby optimizing contact between the surface of the lithium metal anode and the surface of the solid electrolyte for better battery performance. The anode and/or the interface may be formed of a printable lithium composition including lithium metal powder, a polymer binder compatible with the lithium metal powder, a rheology modifier compatible with the lithium metal powder, and a solvent compatible with the lithium metal powder and with the polymer binder. The cathode may be a composite cathode. In another embodiment, the printable lithium composition may be in the form of a foil or film.
US11264597B2
A light emitting structure comprises a bank surrounding a sub-pixel stack on a substrate, a first filler material in an interior space above the sub-pixel stack, and a second filler material over the first filler material. The sub-pixel stack emits a first emission peak along an on-axis direction substantially normal to a top surface of the sub-pixel stack and through an interface between the first and second filler materials. The sub-pixel stack emits a second emission peak along an off-axis direction that is totally internally reflected by the interface before reaching a sloped sidewall of the bank and is then emitted along the on-axis direction. An emissive area of the sub-pixel stack is configured such that the second emission peak is reflected by the interface not more than once before reaching the sloped sidewall.
US11264588B2
There is provided a metal encapsulation structure and a production method thereof, an encapsulation method for a display panel, and a display device. This production method comprises steps of: providing a metal film having a first surface and a second surface opposite to the first surface; forming a silane film on the first surface of the metal film, wherein a surface of the silane film away from the metal film has an active group; and attaching the first surface formed with the silane film to an adhesive layer, so as to react and bond the active group and the adhesive layer.
US11264586B2
The display panel of the present disclosure includes a substrate; an OLED device layer disposed on the substrate and having at least one through hole defined thereon; and a thin film package layer covering the OLED device layer and extending to the at least one through hole. As such, the thin film package layer can be attached to the OLED device layer. Attachment force of the thin film package layer can be enhanced by defining the through hole(s) in the OLED device layer and filling the through hole(s) with the thin film package layer, thereby avoiding phenomenon that films are peeled off.
US11264585B2
The present disclosure provides a flexible display device and a manufacturing method thereof. The flexible display device includes a base substrate; a pixel defining layer disposed on the base substrate defining a plurality of light emitting regions; and a first electrode layer disposed on a side of the pixel defining layer away from the base substrate and in light-emitting regions. A thin film encapsulation layer covers the first electrode layer and has protrusions protruding toward the pixel defining layer at a plurality of positions.
US11264582B2
A light emitting device includes a first light emitting unit and a second light emitting unit. The first light emitting unit includes a first composite layer, and the first composite layer includes an organic light emitting layer. The second light emitting unit is adjacent to the first light emitting unit, the second light emitting unit includes a second composite layer, and the second composite layer includes a quantum dot light emitting layer. A thickness of the first composite layer is different from a thickness of the second composite layer.
US11264581B2
A flexible substrate material having opposed front and back sides and extending in an X-Y plane, the front side being provided with a first electrode layer and further provided with at least one thin film to form at least one thin film device stack; the thin film device stack extending from the X-Y plane in a Z direction perpendicular to the X-Y plane to a distance T; the substrate material having at least one protective structure applied to at least one of the substrate material sides, the first electrode layer and the at least one thin film; the at least one protective structure extending in the Z direction to a distance S from the X-Y plane, the distance S being greater than the distance T.
US11264578B2
A stretchable display device includes a display area having stretchable display units each including first islands on which pixels are disposed and first cut-out grooves between the first islands. A peripheral area is adjacent to the display area, the peripheral area includes stretchable peripheral units each including first lines on which driving circuits are disposed and first opening portions between the first lines. A buffer area is disposed between the display area and the peripheral area. The buffer area includes stretchable buffer units each including second islands, second cut-out grooves between the second islands, second lines connected to the second islands, and second opening portions between the second lines. Shapes of the second cut-out grooves may be different from shapes of the first cut-out grooves, and shapes of the second opening portions may be different from shapes of the first opening portions.
US11264577B2
A display device is disclosed, The display device includes a substrate including a first area, a second area, and a first bending area located between the first and second areas. The first bending area is bent about a first bending axis extending in a first direction. The display device also includes a first inorganic insulating layer arranged over the substrate and having a first opening or a first groove at least in the first bending area, an organic material layer filling at least a part of the first opening or the first groove, and a first conductive layer extending from the first area to the second area across the first bending area and located over the organic material layer.
US11264568B2
The present disclosure includes textured memory cell structures and method of forming the same. In one or more embodiments, a memory cell includes a buffer portion formed on an amorphous portion and an active portion formed on the buffer portion, wherein the active portion is textured with a single out of plane orientation.
US11264558B2
An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.
US11264554B2
High-saturation power Josephson ring modulators and fabrication of the same are provided. A Josephson ring modulator can comprise a plurality of matrix junctions. Matrix junctions of the plurality of matrix junctions can comprise respective superconducting parallel branches that can comprise a plurality of Josephson junctions operatively coupled in a series configuration. A method can comprise forming a first matrix junction comprising arranging a first group of Josephson junctions as first parallel branches. The method can also comprise forming a second matrix junction comprising arranging a second group of Josephson junctions as second parallel branches. Further, the method can comprise forming a third matrix junction comprising arranging a third group of Josephson junctions as third parallel branches. In addition, the method can comprise forming a fourth matrix junction comprising arranging a fourth group of Josephson junctions as fourth parallel branches.
US11264553B2
An overheat detection system and insulation muff comprising an overheat detection system. The overheat detection system comprises a thermometer, a thermal harvesting module comprising at least one passive radiator, the thermal harvesting module being able to generate electrical energy from the thermal difference between two elements, and a digital module, comprising a power management system, a data treatment system and a wireless transmission system, wherein the electrical energy generated by the thermal harvesting module powers the thermometer and the digital module.
US11264543B2
A light conversion film is disclosed. The light conversion film includes a first transparent support layer and a second transparent support layer are formed on upper and lower surfaces of a quantum dot layer, respectively. The quantum dot layer contains 0.4 to 2.0% by weight of quantum dot particles containing 5% by weight or more and less than 35% by weight of cadmium; 0.05 to 0.75% by weight of cadmium-free quantum dot particles; 0.1 to 10% by weight of scattering agent; and 75 to 98% by weight of matrix material, based on the total weight of the quantum dot layer. A backlight unit for a display device including the light conversion film is disclosed.
US11264539B2
A light emitting device (LED) includes an n-doped semiconductor material layer, an active region including an optically active compound semiconductor layer stack configured to emit light located on the n-doped semiconductor material layer, a p-doped semiconductor material layer located on the active region, an anode contact contacting the p-doped semiconductor material layer, a reflector overlying and electrically connected to the anode contact, and a device-side bonding pad layer located on the reflector. The p-doped semiconductor material layer includes an electrically active region that is at least partially covered by the anode contact and an inactive region that an electrical conductivity less than 30% of the electrically active region.
US11264538B2
Disclosed is a Group III nitride semiconductor template for a 300-400 nm near-ultraviolet light emitting semiconductor device, the template including: a growth substrate; a nucleation layer based on AlxGa1-xN (0y); and a monocrystalline Group III nitride semiconductor layer based on AlyGa1-yN (y>0), and a near-ultraviolet light emitting semiconductor device using the template.
US11264532B2
Provided a manufacturing method of a semiconductor light emitting device including forming a plurality of light emitting cells that are separated on a first substrate, forming a first planarization layer by providing an insulating material on the plurality of light emitting cells, forming a second planarization layer by providing a photoresist on the first planarization layer to have a flat upper surface, and soft baking the photoresist, and dry etching the second planarization layer to a predetermined depth to expose a portion of the first planarization layer provided on the plurality of light emitting cells, and a portion of the second planarization layer remaining between the plurality of light emitting cells on the first planarization layer, wherein forming the second planarization layer and dry etching are repeated at least once to remove the portion of the second planarization layer provided between the plurality of light emitting cells.
US11264525B2
A single photon avalanche diode (SPAT) image sensor is disclosed. The SPAT) image sensor include: a substrate of a first conductivity type, the substrate having a front surface and a back surface; a deep trench isolation (DTI) extending from the front surface toward the back surface of the substrate, the DTI having a first surface and a second surface opposite to the first surface, the first surface being level with the front surface of the substrate; an epitaxial layer of a second conductivity type opposite to the first conductivity type, the epitaxial layer surrounding sidewalls and the second surface of the DTI; and an implant region of the first conductivity type extending from the front surface to the back surface of the substrate. An associated method for fabricating the SPAD image sensor is also disclosed.
US11264518B2
A solar cell is fabricated by etching one or more of its layers without substantially etching another layer of the solar cell. In one embodiment, a copper layer in the solar cell is etched without substantially etching a topmost metallic layer comprising tin. For example, an etchant comprising sulfuric acid and hydrogen peroxide may be employed to etch the copper layer selective to the tin layer. A particular example of the aforementioned etchant is a Co-Bra Etch® etchant modified to comprise about 1% by volume of sulfuric acid, about 4% by volume of phosphoric acid, and about 2% by volume of stabilized hydrogen peroxide. In one embodiment, an aluminum layer in the solar cell is etched without substantially etching the tin layer. For example, an etchant comprising potassium hydroxide may be employed to etch the aluminum layer without substantially etching the tin layer.
US11264506B2
A semiconductor device includes a power switch circuit and a logic circuit. The semiconductor device includes a first dielectric layer and a thin film transistor (TFT) formed on the first dielectric layer. The TFT includes a semiconductor nano-sheet, a gate dielectric layer wrapping around a channel region of the semiconductor nano-sheet, and a gate electrode layer formed on the gate dielectric layer. The semiconductor nano-sheet is made of an oxide semiconductor material.
US11264502B2
A method of independently forming source/drain regions in NMOS regions including nanosheet field-effect transistors (NSFETs), NMOS regions including fin field-effect transistors (FinFETs) PMOS regions including NSFETs, and PMOS regions including FinFETs and semiconductor devices formed by the method are disclosed. In an embodiment, a device includes a semiconductor substrate; a first nanostructure over the semiconductor substrate; a first epitaxial source/drain region adjacent the first nanostructure; a first inner spacer layer adjacent the first epitaxial source/drain region, the first inner spacer layer comprising a first material; a second nanostructure over the semiconductor substrate; a second epitaxial source/drain region adjacent the second nanostructure; and a second inner spacer layer adjacent the second epitaxial source/drain region, the second inner spacer layer comprising a second material different from the first material.
US11264500B2
Disclosed herein are structures and techniques for device isolation in integrated circuit (IC) assemblies. In some embodiments, an IC assembly may include multiple transistors spaced apart by an isolation region. The isolation region may include a doped semiconductor body whose dopant concentration is greatest at one or more surfaces, or may include a material that is lattice-mismatched with material of the transistors, for example.
US11264490B2
A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.
US11264489B2
Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack of the NCFET and FE-FET devices includes a non-ferroelectric interfacial layer formed over the semiconductor channel, and a ferroelectric gate dielectric layer formed over the interfacial layer. The ferroelectric gate dielectric layer is formed by inserting dopant-source layers in between amorphous high-k dielectric layers and then converting the alternating sequence of dielectric layers to a ferroelectric gate dielectric layer by a post-deposition anneal (PDA). The ferroelectric gate dielectric layer has adjustable ferroelectric properties that may be varied by altering the precisely-controlled locations of the dopant-source layers using ALD/PEALD techniques. Accordingly, the methods described herein enable fabrication of stable NCFET and FE-FET FinFET devices that exhibit steep subthreshold slopes.
US11264479B2
A method of production of a field-effect transistor from a stack of layers forming a semiconductor-on-insulator type substrate, the stack including a superficial layer of an initial thickness, made of a crystalline semiconductor material and covered with a protective layer, the method including: defining, by photolithography, a gate pattern in the protective layer; etching the gate pattern into the superficial layer to leave a thickness of the layer of semiconductor material in place, the thickness defining a height of a conduction channel of the field-effect transistor; forming a gate in the gate pattern; forming, in the superficial layer and on either side of the gate, source and drain zones, while preserving, in the zones, the initial thickness of the superficial layer.
US11264478B2
A device includes a semiconductor region, an interfacial layer over the semiconductor region, the interfacial layer including a semiconductor oxide, a high-k dielectric layer over the interfacial layer, and an intermixing layer over the high-k dielectric layer. The intermixing layer includes oxygen, a metal in the high-k dielectric layer, and an additional metal. A work-function layer is over the intermixing layer. A filling-metal region is over the work-function layer.
US11264464B2
A silicon carbide device includes a transistor cell with a front side doping region, a body region, and a drift region. The body region includes a first portion having a first average net doping concentration and a second portion having a second average net doping concentration. The first portion and the second portion have an extension of at least 50 nm in a vertical direction. The first average net doping concentration is at least two times the second average net doping concentration, and the first average net doping concentration is at least 1·1017 cm−3.
US11264456B2
The present disclosure describes a fabrication method that prevents divots during the formation of isolation regions in integrated circuit fabrication. In some embodiments, the method of forming the isolation regions includes depositing a protective layer over a semiconductor layer; patterning the protective layer to expose areas of the semiconductor layer; depositing an oxide on the exposed areas the semiconductor layer and between portions of the patterned protective layer; etching a portion of the patterned protective layer to expose the semiconductor layer; etching the exposed semiconductor layer to form isolation openings in the semiconductor layer; and filling the isolation openings with a dielectric to form the isolation regions.
US11264449B2
Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.
US11264446B2
A display apparatus includes: a display panel configured to display an image based on input image data; a gate driver configured to output a gate signal to the display panel; a data driver configured to output a data voltage to the display panel; a driving controller configured to control an operation of the gate driver and an operation of the data driver, to determine a normal driving mode and a low frequency driving mode based on the input image data, and to determine a driving frequency of the display panel based on the input image data; and a touch driver configured to detect a touch event occurring on the display panel, and to output a touch interrupt signal representing the touch event to the driving controller.
US11264444B2
A display apparatus includes a base substrate. A first data line is disposed on the base substrate. A first insulating layer is disposed on both the data line and the base substrate. An amorphous silicon conductive layer is disposed on the first insulating layer. A second insulating layer is disposed on the amorphous silicon conductive layer. A second data line is disposed on the second insulating layer.
US11264441B2
An organic light emitting display apparatus includes a substrate; a thin film transistor which is disposed over the substrate; a first electrode which is disposed over the substrate and electrically connected to the thin film transistor; a passivation layer which covers the thin film transistor and contacts a predetermined region of an upper surface of the first electrode; an intermediate layer which is disposed over the first electrode, includes an organic emission layer, and contacts a predetermined region of the passivation layer; and a second electrode which is disposed over the intermediate layer.
US11264439B2
An organic light-emitting diode (OLED) array substrate and a method of manufacturing the same are disclosed. The OLED array substrate includes a substrate, a thin-film transistor layer, an insulating layer, an anode layer, and a pixel defining layer, wherein the pixel defining layer has a first slot and a second slot. A light-emitting layer is formed in the first slot, and a plurality of fillers are provided in the second slot to form a plurality of discontinuous slots in the second slot for forming a plurality of discontinuous cathode layers. When the cathodes on the surface of the pixel defining layer away from the display area are corroded, the function of the cathodes in the display area would not be affected in such a manner that the display effect of the display device would not be affected.
US11264437B2
A display device includes a substrate, a thin film transistor provided on the substrate, a first electrode connected to the thin film transistor, a second electrode overlapping the first electrode, and a partition wall and a light-emitting device layer provided between the first electrode and the second electrode. The partition wall may include a main chain and a side chain connected to the main chain, and a carbon number of the side chain may be equal to or greater than 14.
US11264435B2
Disclosed is a display device capable of being manufactured through a simplified process and having improved touch sensitivity. The display device includes an encapsulation unit disposed on a light-emitting element, a touch sensor disposed on the encapsulation unit, and an intermediate layer disposed between the encapsulation unit and the touch sensor. The intermediate layer includes a first intermediate layer, having a dielectric constant that is lower than a dielectric constant of an organic film disposed above or under the intermediate layer, and a second intermediate layer, having greater hardness than the first intermediate layer, whereby touch sensitivity is improved while processing is simplified.
US11264434B2
A display device includes a display panel and an input sensing unit disposed on the display panel. The display panel includes a base layer, a first signal line, a light emitting element, a first encapsulation inorganic layer, and a signal pad. The first signal line overlaps a display area and a non-display area and is connected to a transistor disposed in the display area. The first encapsulation inorganic layer is disposed on a second electrode of the light emitting element and overlaps the display area and the non-display area. The signal pad is electrically connected to the first signal line and disposed in the non-display area. The signal pad is connected to the first signal line through a first contact hole defined through the first encapsulation inorganic layer.
US11264431B2
A display panel includes a display region that includes a normal display region and a transparent display region. The normal display region and the transparent display region are connected. The transparent display region includes multiple transparent areas and multiple pixels. The transparent areas have the same shape. For two adjacent transparent areas, a shape of one transparent area has a different placement angle than a shape of another transparent area.
US11264425B2
A process for fabricating an optoelectronic device including an array of germanium-based photodiodes including the following steps: producing a stack of semiconductor layers, made from germanium; producing trenches; depositing a passivation intrinsic semiconductor layer, made from silicon; annealing, ensuring, for each photodiode, an interdiffusion of the silicon of the passivation semiconductor layer and of the germanium of a semiconductor portion, thus forming a peripheral zone of the semiconductor portion, made from silicon-germanium.
US11264422B2
A position-sensitive photodetector device includes a grid of series-connected photodetectors that are electrically coupled to either a vertical photodetector array (VA photodetectors) or to a horizontal photodetector array (HA photodetectors). The VA and HA photodetectors are arranged in an alternating sequence along rows and/or columns throughout the grid. A horizontal-position readout line is electrically coupled to a termination of each vertical photodetector array, and a vertical-position readout line is electrically coupled to a termination of each horizontal photodetector array.
US11264419B2
A fully depleted silicon on insulator (FDSOI) is employed to reduce diffusion leakage (e.g., gate induced drain leakage, junction leakage, etc.) associated with the diffusion regions of a pixel cell. The buried oxide (BOX) layer, for example, fully isolates the transistor channel region, such as an (N) channel region of the pixel cell from the photodiode(s) of the pixel region, eliminating the junction leakage path, thus leading to a reduction in diffusion leakage and an increase device operation speed. An increase of full well capacity can also be realized by the absence of isolation structure, such as trench isolation or isolation implant structure.
US11264418B2
A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.
US11264416B2
An image processing apparatus comprises means for selecting, from a single image, a range where a target pixel is made to be a reference, means for approximating a distribution of pixel values of the selected range by a function that represents a curved surface, and means for calculating a vector related to the distribution of pixel values from a parameter of the function obtained as a result of the approximation.
US11264398B2
According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.
US11264396B2
Various embodiments of the present application are directed to an IC device and associated forming methods. In some embodiments, a memory region and a logic region are integrated in a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices disposed on a plurality of logic sub-regions of the logic region. A first logic device is disposed on a first upper surface of a first logic sub-region. A second logic device is disposed on a second upper surface of a second logic sub-region. A third logic device is disposed on a third upper surface of a third logic sub-region. Heights of the first, second, and third upper surfaces of the logic sub-regions monotonically decrease. By arranging logic devices on multiple recessed positions of the substrate, design flexibility is improved and devices with multiple operation voltages are better suited.
US11264395B1
A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.
US11264393B2
A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
US11264392B2
A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.
US11264389B2
The stack capacitor structure includes a substrate, first, second, third, and fourth support layers, first, second, and third insulating layers, first, second, and third holes, and a capacitor. The first support layer is disposed over the substrate. The first insulating layer is disposed on the first support layer. The second support layer is disposed on the first insulating layer. The third support layer is disposed on the second support layer. The second insulating layer is disposed on the third support layer. The third insulating layer is disposed on the second insulating layer. The fourth support layer is disposed on the third insulating layer. The first hole penetrates through from the second support layer to the first support layer. The second and third holes penetrate through from the fourth support layer to the third support layer. The capacitor is disposed in the first, second, and third holes.
US11264385B2
The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.
US11264368B2
Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first dielectric structure having first inner sidewalls over an interlayer dielectric (ILD) structure. A second dielectric structure is over the first dielectric structure, where the first inner sidewalls are between second inner sidewalls of the second dielectric structure. A sidewall barrier structure is over the first dielectric structure and extends vertically along the second inner sidewalls. A lower bumping structure is between the second inner sidewalls and extends vertically along the first inner sidewalls and vertically along third inner sidewalls of the sidewall barrier structure. An upper bumping structure is over both the lower bumping structure and the sidewall barrier structure and between the second inner sidewalls, where an uppermost point of the upper bumping structure is at or below an uppermost point of the second dielectric structure.
US11264364B2
A display device including a first sub-pixel and a second sub-pixel is provided. The first sub-pixel includes a first light emitting unit and a first wavelength conversion layer disposed thereon. The first sub-pixel provides a first light emitted from the first light emitting unit and converted by the first wavelength conversion layer. The first light includes a first main-peak and a first sub-peak. The second sub-pixel includes a second light emitting unit and a second wavelength conversion layer disposed thereon. The second sub-pixel provides a second light emitted from the second light emitting unit and converted by the second wavelength conversion layer. The second light includes a second main-peak and a second sub-peak. A first wavelength difference between the first main-peak and the second main-peak is less than 20 nm, and the first wavelength difference is less than a second wavelength difference between the first sub-peak and the second sub-peak.
US11264363B2
A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure, a redistribution line, and a seal ring structure. The redistribution line and the seal ring structure are in the dielectric structure, the seal ring structure continuously surrounds the redistribution line, the seal ring structure includes a first seal ring and a second seal ring over and electrically connected to the first seal ring, and the redistribution structure has a first sidewall, a first surface, and a second surface opposite to the first surface. The chip package structure includes a chip structure over the first surface. The chip package structure includes a ground bump over the second surface. The chip package structure includes a conductive shielding film covering the chip structure and the first sidewall of the redistribution structure.
US11264362B2
A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die. The redistribution circuit structure is electrically connected with the first and second semiconductor dies, and the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure.
US11264352B2
An electronic package structure and a chip thereof are provided. The electronic package structure includes a substrate, a chip, a plurality of signal wires, and a core ground wire. The chip disposed on and electrically connected to the substrate has a core wiring region and an input and output pad region located at a top surface thereof. The input and output pad region is located between the core wiring region and an edge of the chip. The chip includes a plurality of signal pads in the input and output region and a core ground pad adjacent to one of the signal pads. The core ground pad located in the core wiring region. The signal wires are respectively connected to the signal pads. The core ground wire connected to the core ground pad is adjacent to and shields one of the signal wires.
US11264351B2
A method of manufacturing a chip module comprises a step of disposing a first electronic element 13 on a first jig 500, a step of disposing a first connector 60 on the first electronic element 13 via a conductive adhesive 5, a step of disposing a second electronic element 23 on the first connector 60 via a conductive adhesive 5, a step of disposing a second connector 70 on a second jig 550, a step of reversing the second jig in a state where the second connector 70 is fixed to the second jig 550 and disposing the second connector 70 on the second electronic element 23 via a conductive adhesive 5, and a step of curing the conductive adhesives 5.
US11264337B2
A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die and a frame. The semiconductor die is disposed over the substrate. The frame is disposed over the substrate, wherein the frame is adjacent to the semiconductor die, and the upper surface of the frame is lower than the upper surface of the semiconductor die.
US11264333B2
The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.
US11264330B2
Disclosed are a chip package capable of improving the strength of a package and simplifying a manufacturing process and a manufacturing method therefor. This invention may improve the durability of the package by further forming a reinforcing layer on a chip by using an adhesive layer and molding the chip and the reinforcing layer so as to be integrated by using a molding layer. Also, the strength of the package may be improved by having a structure in which solder balls are formed between a base substrate and a re-wiring layer and integrated with the molding layer, and a wiring layer may be formed directly on the molding layer by using polyimide (PI) as the molding layer without using a separate insulating layer formed on the molding layer as in the conventional art.
US11264329B2
An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.
US11264310B2
A method includes attaching semiconductor dies to die attach pads of first and second columns of the lead frame; enclosing the semiconductor dies of the respective columns in respective first and second package structures; trimming the lead frame to separate respective first and second lead portions of adjacent ones of the first and second columns of the lead frame; moving the first columns along a column direction relative to the second columns; and separating individual packaged electronic devices of the respective first and second columns from one another.
US11264309B2
A semiconductor package includes at least one die attach pad of a leadframe, at least one semiconductor die mounted on the at least one die attach pad; and a plurality of lead terminals disposed around the at least one die attach pad and electrically connected to respective input/output (I/O) pads on the at least one semiconductor die through a plurality of bond wires. The plurality of lead terminals comprises first lead terminals, second lead terminals, and third lead terminals, which are arranged in triple row configuration along at least one side of the semiconductor package. Each of the first lead terminals, second lead terminals, and third lead terminals has an exposed base metal on a cut end thereof.
US11264301B2
A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.
US11264300B2
A package structure and method for forming the same are provided. The package structure includes a semiconductor die formed over a first side of an interconnect structure, and the semiconductor die has a first height. The package structure also includes a first stacked die package structure formed over the first side of the interconnect structure, and the first stacked die package structure has a second height. The second height is greater than the first height. The package structure includes a lid structure formed over the semiconductor die and the first stacked die package structure. The lid includes a main portion and a protruding portion extending from the main portion, and the protruding portion is directly over the semiconductor die.
US11264296B2
An electrical component package includes a glass substrate, an interposer panel positioned on the glass substrate, the interposer panel comprising a device cavity, a wafer positioned on the interposer panel such that the device cavity is enclosed by the glass substrate, the interposer panel, and the wafer. The electrical component package further includes a metal seed layer disposed between the interposer panel and the wafer, and a dielectric coating. The dielectric coating hermetically seals the interposer panel to the glass substrate, the interposer panel to the metal seed layer and the wafer, and the interposer panel hermetically seals the metal seed layer to the glass substrate such that the device cavity is hermetically sealed from ambient atmosphere.
US11264295B2
Integrated circuit substrates having features for containing liquid adhesive, and methods for fabricating such substrates, are provided. A device can include a first substrate layer and a second substrate layer adhered to the first substrate layer such that a portion of the top surface of the first substrate layer is exposed to define a bottom of a cavity, and an edge of the second substrate layer adjacent to the exposed top surface of the first substrate layer defines an edge of the cavity. The device can include an integrated circuit die adhered to the exposed top surface of first substrate layer with a liquid adhesive. The first substrate layer can define a trench in the bottom of the cavity between a region of the integrated circuit die and the edge of the cavity such that the trench can receive bleed-out of the liquid adhesive from between the integrated circuit die and the top surface of the first substrate layer.
US11264293B2
A wiring board includes an insulating substrate and a wiring conductor. The insulating substrate includes a first layer having an upper surface and a lower surface and having a first content of aluminum oxide and containing mullite and a second layer stacked on the upper surface and/or the lower surface of the first layer and having a second content of aluminum oxide greater than the first content. The wiring conductor is located inside the first layer and contains a manganese compound and/or a molybdenum compound. A manganese silicate phase and/or a magnesium silicate phase in an interface area between the insulating substrate and the wiring conductor.
US11264290B2
A TMR element includes a reference layer, a magnetization free layer, a tunnel barrier layer between the reference layer and the magnetization free layer, and a perpendicular magnetization inducing layer and a leakage layer stacked on a side of the magnetization free layer opposite to the tunnel barrier layer side. A magnetization direction of the reference layer is fixed along a stack direction. The perpendicular magnetization inducing layer imparts magnetic anisotropy along the stack direction to the magnetization free layer. The leakage layer is disposed on an end portion region in an in-plane direction of the magnetization free layer. The perpendicular magnetization inducing layer is disposed on at least a central region in the in-plane direction of the magnetization free layer. A resistance value of the leakage layer along the stack direction per unit area in plane is less than that of the perpendicular magnetization inducing layer.
US11264287B2
An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.
US11264286B2
Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.
US11264276B2
A method is presented for forming self-aligned vias by employing a top level line pattern. The method includes forming first conductive lines within a first dielectric material, recessing one conductive line of the conductive lines to define a first opening, filling the first opening with a second dielectric material, and forming a sacrificial block perpendicular to and in direct contact with a non-recessed first conductive line. The method further includes forming a single via directly underneath the sacrificial block by recessing the non-recessed first conductive line, removing the sacrificial block to define a second opening, and filling the second opening with a conductive material to define a second conductive line such that the single via aligns to both the non-recessed first conductive line and the second conductive line.
US11264267B2
A substrate processing apparatus includes a stage, a light source, an optical assembly, a light receiver, and controller circuitry. The stage includes a first placing surface on which a substrate is to be placed, and a second placing surface that surrounds the first placing surface and on which a focus ring is to be placed. The optical assembly focuses light from the light source on a lower surface position, which is a position of a lower surface of the focus ring placed on the second placing surface. The light receiver receives light from the lower surface position. The controller circuitry detects at least one of a presence and an absence of the focus ring on the second placing surface, based on light received by the light receiver.
US11264259B2
A workpiece conveyance apparatus having: a conveyance path on which the workpiece moves; a gas flotation section that gas-floats the workpiece over the conveyance path; a movable holding section that holds the workpiece to move on the conveyance path along with the workpiece; and a treatment region conveyance path that is located on the conveyance path, and has a treatment region where predetermined treatment for the workpiece is performed, wherein the movable holding section has at least two or more holding sections along a movement direction of the conveyance path, each of the holding sections is capable of switching between release of holding and holding for the workpiece during movement of the workpiece, operation for releasing holding of the workpiece by the holding section on the treatment region conveyance path, and holding the workpiece on the conveyance path other than the treatment region conveyance path.
US11264256B2
Provided is a wafer inspection apparatus including a monochromator that extracts monochromatic light, a collimator that outputs the monochromatic light as parallel light, a first polarization assembly that polarizes the parallel light and radiates the polarized light to a wafer, an imaging optical system that condenses light reflected from the wafer, a spectroscope that splits the condensed light into a plurality of spectrums, a first lens that condenses the plurality of spectrums, a second polarization assembly that outputs the plurality of spectrums as a plurality of polarized lights having different diffraction orders and a difference of 90°, a second lens that condenses the plurality of polarized lights, a third polarization assembly that outputs common polarized light based on the plurality of polarized interfering with each other, a camera that generates a phase difference image based on the common polarized light, and a signal processor that analyzes the phase difference image.
US11264254B2
A substrate processing tool configured for performing integrated substrate processing and substrate metrology, and methods of processing a substrate. The substrate processing tool includes a substrate transfer chamber, a plurality of substrate processing chambers coupled to the substrate transfer chamber, and a substrate metrology module coupled to the substrate transfer chamber. A substrate processing method includes processing a substrate in a first substrate processing chamber of a substrate processing tool, transferring the substrate from the first substrate processing chamber through a substrate transfer chamber to a substrate metrology module in the substrate processing tool, performing metrology on the substrate in the substrate metrology module, transferring the substrate from the substrate metrology module to a second substrate processing chamber through the substrate transfer chamber, and processing the substrate in the second substrate processing chamber.
US11264245B2
Provided is a method for manufacturing a semiconductor device that improves the reliability of the semiconductor device under thermal stress and the assembly performance of the semiconductor device in manufacturing steps. The method includes the following: forming a first electrode by depositing a first conductive film onto one main surface of a semiconductor substrate and patterning the first conductive film; forming a first metal film corresponding to a pattern of the first electrode onto the first electrode; forming a second electrode by depositing a second conductive film onto the other main surface of the semiconductor substrate; forming a second metal film thinner than the first metal film onto the second electrode; and collectively forming a third metal film onto each of the first metal film and the second metal film by electroless plating.
US11264244B2
After a MISFET is formed on a substrate including a semiconductor substrate, an insulating layer and a semiconductor layer, an interlayer insulating film and a first insulating film are formed on the substrate. Also, after an opening is formed in each of the first insulating film and the interlayer insulating film, a second insulating film is formed at each of a bottom portion of the opening and a side surface of the opening and also formed on an upper surface of the first insulating film. Further, each of the second insulating film formed at the bottom portion of the opening and the second insulating film formed on the upper surface of the first insulating film is removed by etching. After that, an inside of the opening is etched under a condition that each of the first insulating film and the second insulating film is less etched than the insulating layer.
US11264243B2
A diffuser includes a diffuser element made of silicon carbide having conductivity, conductive holding members for holding the diffuser element, conductive gaskets that seal between the diffuser element and the holding members. Static electricity on the diffuser element is eliminated through the gaskets, and the holding members.
US11264231B2
A method for manufacturing a backside metalized compound semiconductor wafer includes the steps of: providing a compound semiconductor wafer; attaching the compound semiconductor wafer to a supporting structure; forming an adhesion layer including nickel and vanadium on a back surface of the compound semiconductor wafer; forming an alloy layer including titanium and tungsten on the adhesion layer; forming a metallization layer including gold on the alloy layer; and removing the supporting structure from the compound semiconductor wafer to obtain the backside metalized compound semiconductor wafer.
US11264222B2
Systems and methods are described for heating sample transfer lines between a source of a sample and a detection system to detect analytes of interest in the sample, where the sample is maintained in a heated state to maintain dissolved analytes of interest in solution.
US11264221B2
The present invention relates to the high resolution imaging of samples using imaging mass spectrometry (IMS) and to the imaging of biological samples by imaging mass cytometry (IMCTM) in which labelling atoms are detected by IMS. LA-ICP-MS (a form of IMS in which the sample is ablated by a laser, the ablated material is then ionised in an inductively coupled plasma before the ions are detected by mass spectrometry) has been used for analysis of various substances, such as mineral analysis of geological samples, analysis of archaeological samples, and imaging of biological substances. However, traditional LA-ICP-MS systems and methods may not provide high resolution. Described herein are methods and systems for high resolution IMS and IMC.
US11264216B2
The present invention relates to an arc vaporization source for generating hard surface coatings on tools. The invention comprises an arc-vaporization source, comprising at least one electric solenoid and a permanent magnet arrangement that is displaceable relative to the target surface. The vaporization source can be adjusted to the different requirements of oxide, nitride, or metal coatings. The rate drop during the lifespan of a target to be vaporized can be held constant or adjusted by suitably adjusting the distance of the permanent magnets to the front side of the target. A compromise between the coating roughness and rate can be set.
US11264212B1
A measurement system for a plasma processing system includes a detector and an ion current meter coupled to the ion current collector and configured to provide a signal based on the measurements from the ion current collector. The detector includes an insulating substrate including a cavity, an ion angle selection grid configured to be exposed to a bulk plasma disposed in an upper portion of the cavity, and an ion current collector disposed within the cavity at an opposite side of the cavity below the ion angle selection grid. The ion angle selection grid includes an ion angle selection substrate and a plurality of through openings extending through the ion angle selection substrate, where each of the plurality of through openings has a depth into the ion angle selection substrate and a width orthogonal to the depth, where a ratio of the depth to the width is greater than or equal to 40.
US11264205B2
A method, including using an implant recipe to perform an implant by scanning an ion beam along a first axis over a substrate, coated with a photoresist layer, while the substrate is scanned along a perpendicular axis; measuring an implant current (I) during the implant, using a first detector, positioned to a side of a substrate position; determining a value of a difference ratio (I−B)/(B), based upon the implant current, where B is current measured by the first detector, during a calibration at base pressure; determining a plurality of values of a current ratio (CR) for the plurality of instances, based upon the difference ratio, the current ratio being a ratio of the implant current to a current measured by a second detector, positioned over the substrate position, during the calibration; and adjusting scanning the ion beam, scanning of the substrate, or a combination thereof, based upon the current ratio.
US11264202B2
A method, a non-transitory computer readable medium and a three-dimensional evaluation system for providing three dimensional information regarding structural elements of a specimen. The method can include illuminating the structural elements with electron beams of different incidence angles, where the electron beams pass through the structural elements and the structural elements are of nanometric dimensions; detecting forward scattered electrons that are scattered from the structural elements to provide detected forward scattered electrons; and generating the three dimensional information regarding structural elements based at least on the detected forward scattered electrons.
US11264201B2
A charged particle beam device includes: a charged particle beam source configured to generate a charged particle beam with which a sample is irradiated; a charged particle detection unit configured to detect a charged particle generated when the sample is irradiated with the charged particle beam; an intensity data generation unit configured to generate intensity data of the charged particle detected by the charged particle detection unit; a pulse-height value data generation unit configured to generate pulse-height value data of the charged particle detected by the charged particle detection unit; and an output unit configured to output a first image of the sample based on the intensity data and a second image of the sample based on the pulse-height value data.
US11264199B2
A microfluidic cell system to measure proton concentration in a fluid sample. The microfluidic cell system includes: a first microchip and a second microchip dimensioned to permit electron beam scanning of a fluid sample; a first membrane attached to the first microchip; a second membrane attached to the second microchip, the first membrane and the second membrane being disposed adjacent to one another with a space for the fluid sample therebetween, and the first membrane and the second membrane including a region of the fluid sample in which an electron beam is scanned; a first electrode patterned onto the first membrane and positioned a first distance from the region; a second electrode patterned onto the first microchip and positioned a second distance from the region, the first distance being less than the second distance; and a potentiostat in communication with the first electrode and the second electrode.
US11264198B2
An objective lens arrangement that may include a magnetic lens and an electrostatic lens. The magnetic lens may include one or more coils, an upper polepiece and a lower polepiece. The electrostatic lens may include an upper electrode, an internal lower electrode and an external lower electrode. A majority of the internal lower electrode may be surrounded by a majority of the external lower electrode. The upper electrode, the internal lower electrode, and the external lower electrode are arranged in a coaxial relationship along an optical axis of the objective lens arrangement. An area of a bottom aperture of the external lower electrode may not exceed an area of a bottom aperture of the internal lower electrode.
US11264191B2
A breaker includes a stationary contact, a movable contact, an operation device including a link portion liked to the movable contact and including an output lever rotatably supported, the operation device operating rotation of the output lever in accordance with a first control signal for a command for pulling out the movable contact and a second control signal for a command for inserting the movable contact, and an auxiliary contact to switch between turn-on and turn-off of an input of the first control signal and the second control signal to the operation device in conjunction with operation of the output lever, the auxiliary contact being able to be used in a circuit configuration to monitor a state of the operation device. The output lever rotates so as to operate a first link portion on a side toward a first direction with respect to a rotational center of the output lever.
US11264190B2
A system including ruggedized optic fiber cable assembly for use with an arc detection relay to protect electrical components from faults resulting in an arc flash. The cable assembly includes a pair of ruggedized ST connectors located at opposite ends of a ruggedized optical fiber cable. The cable includes an optical fiber core surrounded by a transparent gel layer and a transparent jacket surrounding the gel layer. Each ST connector includes a boot formed of a resilient material to provide shock absorption for the portion of the optical fiber cable extending through it. An accessory electronic cable is also provided, as are couplers, adapters for mounting the couplers onto walls, and sleeves with air pockets to enhance the ruggedness of the cable at points of stress, e.g., bends.
US11264187B2
A control device configured for use in a load control system to control an external electrical load may provide simple feedback regarding the operation of the control device. For example, the control device may comprise a base portion configured to be mounted to an electrical wallbox or over a mechanical switch, and a control unit connected to the base portion. The control unit may comprise a rotation portion rotatable with respect to the base portion, an actuation portion, and a light source. The control unit may be configured to control the light source to illuminate at least an illuminated portion of the actuation portion in response to actuations of the rotation portion and the actuation portion. In addition, the control unit may provide a limit indication on the illuminated portion by blinking the illuminated portion when the electrical load has reached a limit.
US11264185B2
A restoration assembly of a button switch includes first and second sleeves, and a spring disposed between the two sleeves. A first outer diameter of the first sleeve is less than a second inner diameter of the second sleeve to make the second sleeve movably jacket outside the first sleeve. The jacketed first and second sleeves are disposed between a key cap and a base of the button switch. The spring has a first end portion, a second end portion and a middle section. A middle outer diameter of the middle section of the spring is larger than a first inner diameter of the first sleeve. During the spring being compressed along with the key cap being pressed downward, the middle section is squeezed to shrink and slide into the first sleeve through an end edge of the first sleeve, thereby producing a tactile feedback and/or a first sound.
US11264183B2
The invention relates to a center break switch having a contact system for electrical current conduction and bus transfer switching. The contact system includes two moving contacts. One of the two moving contacts includes a finger contact and the other moving contact includes a first contact. Each moving contact includes a contact for bus transfer switching, wherein one of the two contacts includes a spherical contacting element, and the other contact includes a rectangular contacting element. The spherical contacting element and the rectangular contacting element engage during switching for the bus transfer, and stay in contact when the finger contact is engaged with the first contact for electrical current conduction.
US11264177B2
A method includes producing a ceramic body including a stack of a dielectric layer and an internal electrode, applying a conductive paste including metal powder and glass frit to an outer surface of the ceramic body and baking the conductive paste to form a base external electrode layer, forming a crack in glass exposed to an outer surface of the base external electrode layer, after the formation of the crack, applying a water repellent to the base external electrode layer, and forming a Ni plating layer and a Sn plating layer on the base external electrode layer.
US11264170B2
A capacitor component includes a body including dielectric layers, first and second internal electrodes, laminated in a first direction, facing each other, and first and second cover portions, disposed on outermost portions of the first and second internal electrodes, and first and second external electrodes, respectively disposed on both external surfaces of the body in a second direction, perpendicular to the first direction, and respectively connected to the first and second internal electrodes. An indentation including a glass is disposed at at least one of boundaries between the first internal electrodes and the first external electrode or one of boundaries between the second internal electrodes and the second external electrode.
US11264169B2
A capacitor insulation system is disclosed in the present application. The insulation system includes a dielectric fluid containing a first voltage stabilizing additive of a first concentration. The insulation system further includes a dielectric film containing the first voltage stabilizing additive of a second concentration and impregnated in the dielectric fluid. The first concentration is greater than the second concentration. The insulation system prepared according to the present disclosure can provide an increased and quite stable dielectric strength.
US11264166B2
An interposer includes an interposer body; first and second lower patterns spaced apart from each other on a lower surface of the interposer body; and first and second upper patterns spaced apart from each other on an upper surface of the interposer body. The first and second upper patterns include first and second shape-securing layers spaced apart from each other on the upper surface of the interposer body, and first and second acoustic noise reduction layers disposed on the first and second shape-securing layers, respectively. An electronic component includes a capacitor and the interposer.
US11264161B2
A coil electronic component includes a support substrate, a coil pattern disposed on at least one surface of the support substrate, a lead-out pattern disposed on at least one surface of the support substrate to be connected to the coil pattern, an encapsulant disposed to encapsulate the support substrate, the coil pattern, and at least one portion of the lead-out pattern, and an external electrode disposed on an external surface of the encapsulant to be connected to the lead-out pattern. The lead-out pattern includes a slit disposed on a side of a region facing the external electrode. The slit is exposed in a direction toward the external electrode and in a direction away from the support substrate, on the basis of a thickness direction of the support substrate, and is not connected to the support substrate.
US11264156B2
A magnetic core includes a nanocrystalline alloy ribbon having a composition represented by FeCuxBySizAaXb, where 0.6≤x<1.2, 10≤y≤20, 0≤(y+z)≤24, and 0≤a≤10, 0≤b≤5, all numbers being in atomic percent, with the balance being Fe and incidental impurities, and where A is an optional inclusion of at least one element selected from Ni, Mn, Co, V, Cr, Ti, Zr, Nb, Mo, Hf, Ta and W, and X is an optional inclusion of at least one element selected from Re, Y, Zn, As, In, Sn, and rare earth elements. The nanocrylstalline alloy ribbon has a local structure such that nanocrystals with average particle sizes of less than 40 nm are dispersed in an amorphous matrix and are occupying more than 30 volume percent of the ribbon.
US11264151B2
A superconducting wire includes a multilayer stack and a covering layer (stabilizing layer or protective layer). The multilayer stack includes a substrate having a main surface and a superconducting material layer formed on the main surface. The covering layer (stabilizing layer or protective layer) is disposed on at least the superconducting material layer. A front surface portion of the covering layer (stabilizing layer or protective layer) located on the superconducting material layer (front surface portion of the stabilizing layer or upper surface of the protective layer) has a concave shape.
US11264146B2
Disclosed is a flat cable with an improved function of preventing a short phenomenon that may occur when the flat cable is incorrectly inserted into a connector. The flat cable according to an embodiment of the present disclosure is a flat cable extending straight in a direction and having a front end that is inserted and connected to an external connector, and includes a plurality of conductors extending straight along a lengthwise direction of the flat cable, spaced apart a predetermined distance in a widthwise direction of the flat cable, and a cable body made of an insulating material, and extending straight along the lengthwise direction of the flat cable, wherein the conductors are mounted on at least one surface.
US11264144B2
A thermionic energy conversion system, preferably including one or more electron collectors, interfacial layers, encapsulation, and/or electron emitters. A method for manufacturing the thermionic energy conversion system. A method of operation for a thermionic energy conversion system, preferably including receiving power, emitting electrons, and receiving the emitted electrons, and optionally including convectively transferring heat.
US11264133B2
Methods and devices and systems including a communication module operatively coupled to a data collection module for communicating the stored analyte related data after the analyte related data is stored in the data collection module over a predetermined time period, and a user interface unit configured to communicate with the communication module to receive from the communication module the stored analyte related data in the data collection module over the predetermined time period, and to output information associated with the monitored analyte level, where the user interface unit is configured to operate in a prospective analysis mode including substantially real time output of information associated with the monitored analyte level, or a retrospective analysis mode including limited output of information during the predetermined time period wherein no information related to the monitored analyte level is output during the predetermined time period, are provided.
US11264131B2
A vital-signs patch for a patient monitoring system is disclosed. The patch consists of a housing that is configured to be worn on the skin of a patient. The housing contains a radio, one or more sensor interfaces, a processor, and a battery. The processor can selectably turn portions of the processor off and on and selectably turn power off and on to at least a portion of the sensor interfaces and radio. The processor includes a timer that, each time the timer times out, will turn all the parts of the processor on and start a new timing period. When the processor receives a signal, the processor will turn off power to at least a portion of the processor and at least a portion of the sensor interfaces.
US11264124B2
Item-management systems, apparatus, and methods are described, preferably for management of items such as medicaments. In embodiments, an item-management system comprises a container defining plural cells, a docking station configured to receive the container, sources of visible information to indicate the cell(s) into which an item is to be loaded, and at least one controller operable to control the visible information sources to indicate the cell into which the item is to be received.
US11264123B2
A computer-implemented system includes a treatment apparatus configured to be manipulated by a patient while performing a treatment plan and a server computing device configured to execute an artificial intelligence engine to generate the treatment plan and a billing sequence associated with the treatment plan. The server computing device receives information pertaining to the patient, generates, based on the information, the treatment plan including instructions for the patient to follow, and receives a set of billing procedures associated with the instructions. The set of billing procedures includes rules pertaining to billing codes, timing, constraints, or some combination thereof. The server computing device generates, based on the set of billing procedures, the billing sequence for at least a portion of the instructions. The billing sequence is tailored according to a certain parameter. The server computing device transmits the treatment plan and the billing sequence to a computing device.
US11264122B2
A system for mobile carrier-centric data record custodians is provided and includes cellular network interfaces that transmit and receive wireless communication over a cellular network, an electronic medical record (EMR) database that stores EMRs, and a mobile account management server coupled with the cellular network interfaces and the EMR database, the mobile account management server receiving an EMR request associated with a mobile user account over the cellular network, querying the EMR database for a results set having EMRs satisfying the query, generating a plurality of EMR responses to the EMR request as a function of the results set and state information associated with the cellular network, and transmitting the plurality of EMR responses over the plurality of cellular network interfaces to the mobile device via the cellular network, the plurality of EMR responses being formatted for wireless protocols of the cellular network interfaces over which they are transmitted.
US11264119B2
A genomic data translation system can be configured to process next-generation sequencing information. The system can receive an output file including raw genome data. The system can parse the output file to determine segments corresponding to individual chromosomes. The system can identify ranges of nucleotides and determine the first set of genes included in a human reference genome listing that fall within the ranges. The system can also maintain a gene list of genes, and determine a matched set of genes that are included in the gene list and the first set of genes. The system can generate a configurable text string including non-configurable regions and configurable regions. The configurable regions can be populated with text based on the raw genomic data, a set of translation rules, and a set of translation text strings.
US11264115B2
An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.
US11264111B2
An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.
US11264106B2
A semiconductor memory device includes separate first and second word lines respectively facing first and second portions of a semiconductor and sandwiching the semiconductor; and first and second cell transistors respectively located in the first and second portions and respectively coupled to the first and second word lines. In a first operation, a first read is executed on the second cell transistor while a first voltage and a higher second voltage are being respectively applied to the first and second word lines. In a second operation, a second read is executed on the first cell transistor while a third voltage between the first and second voltages is being applied to the second word line.
US11264103B2
A computer-implemented method, according to one embodiment, includes: determining a current operating state of a block of memory. The block includes more than one type of page therein, and at least one read voltage is associated with each of the page types. The current operating state of the block is further used to produce a hybrid calibration scheme for the block which identifies a first subset of the read voltages, and a second subset of the read voltages. The read voltages in the second subset are further organized in one or more groupings. A unique read voltage offset value is calculated for each of the read voltages in the first subset, and a common read voltage offset value is also calculated for each grouping of read voltages in the second subset.
US11264097B2
A voltage generation circuit includes a driver configured to generate an internal voltage by driving an external voltage depending on a driving signal; an amplifier configured to generate the driving signal depending on a result of comparing a reference voltage and a feedback voltage; and a switch configured to delay a decrease of the internal voltage by precharging a node of the amplifier with a predetermined voltage depending on a control signal.
US11264092B2
A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit and a judging circuit. The cell array includes plural multi-level memory cells in an m×n array. The cell array is connected with m word lines and n lines. The current supply circuit provides one of plural reference currents according to a current control value. The path selecting circuit is connected with the current supply circuit and the n bit lines. The judging circuit is connected with the path selecting circuit, and generates n output data. A first path selector of the path selecting circuit is connected with a path selecting circuit and a first bit line. A first judging device of the judging circuit is connected with the first path selector and generates a first output data.
US11264091B1
An operating method and a non-volatile memory device are provided. The non-volatile memory device includes a memory array including a plurality of memory cells. The operating method includes applying a first program voltage signal to selected word lines connected to selected memory cells during a first program period and measuring a first threshold voltage, applying a second program voltage signal to the selected word lines during a second program period and measuring a second threshold voltage, applying a test bit line voltage signal to selected bit lines and applying a third program voltage signal to the selected word lines during a third program period and measuring a third threshold voltage and determining the enhanced bit line voltage by comparing a difference between the third threshold voltage and the second threshold voltage with a difference between the second threshold voltage and the first threshold voltage.
US11264087B2
A semiconductor device includes a first wiring having a first portion, a second portion, a third portion provided between the first portion and the second portion, memory cells connected to the third portion of the first wiring, a field effect transistor having a drain connected to the second portion, and a gate, and a second wiring provided in parallel with the first wiring. The third portion of the first wiring includes a fourth portion located nearest to the first portion and a fifth portion located nearest to the second portion. The first wiring further includes a sixth portion disposed between the first portion and the fourth portion. The memory cells include a first memory cell connected to the fourth portion and a second memory cell connected to the fifth portion. The second wiring is electrically connected between the sixth portion and the gate of the field effect transistor.
US11264084B2
A flash memory device includes: first pads; second pads; third pads; a memory cell array; a row decoder block; a buffer block that stores a command and an address received from an external semiconductor chip through the first pads and provides the address to the row decoder block; a page buffer block that is connected to the memory cell array through bit lines, is connected to the third pads through data lines, and exchanges data signals with the external semiconductor chip through the data lines and the third pads; and a control logic block that receives the command from the buffer block, receives control signals from the external semiconductor chip through the second pads, and controls the row decoder block and the page buffer block based on the received command and the received control signals.
US11264082B2
A memory device comprises a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data, where N is a natural number, and a first peripheral circuit for controlling the first memory cells according to an N-bit data access scheme and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells according to an M-bit data access scheme and disposed below the second memory cell array, wherein the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight, wherein the plurality of first memory cells and the plurality of second memory cells are included in a first chip having a first metal pad, the first peripheral circuit and the second peripheral circuit are included in a second chip having a second metal pad, and the first chip and the second chip are vertically connected to each other by the first metal pad and the second metal pad.
US11264079B1
Apparatuses, systems, and methods for row hammer based cache lockdown. A controller of a memory may include an aggressor detector circuit which determines if addresses are aggressor addresses or not. The controller may include a tracker circuit which may count a number of times an address is identified as an aggressor, and may determine if the aggressor address is a frequent aggressor address based on the count. If the address is a frequent aggressor address, a cache entry associated with the frequent aggressor address may be locked (e.g., for a set amount of time). In some embodiments, the controller may include a second tracker which may determine if the frequent aggressor address is a highly attacked address. An address mapping associated with the highly attacked address may be changed.
US11264076B2
A power control circuit includes a power control signal generation circuit configured to generate a voltage control signal according to a deep sleep command for operating a semiconductor apparatus in a deep sleep mode; a voltage divider circuit having a division ratio that is changed according to the voltage control signal, and configured to generate a divided voltage by dividing an internal voltage at the changed division ratio; a comparator configured to generate a detection signal by comparing a reference voltage to the divided voltage; an oscillator configured to generate an oscillation signal according to the detection signal; and a pump configured to generate the internal voltage according to the oscillation signal.
US11264075B2
Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.
US11264061B2
According to one embodiment, a method of controlling a memory device includes supplying a second potential having a first value to a second electrode and simultaneously, or thereafter, supplying a third potential to a third electrode, and thereafter stopping supply of the third potential such that the potential of the third electrode decays while reducing the potential of the second electrode, and thereafter supplying a first potential to the first electrode.
US11264043B2
An apparatus for encoding a speech signal by determining a codebook vector of a speech coding algorithm is provided. The apparatus includes a matrix determiner for determining an autocorrelation matrix R, and a codebook vector determiner for determining the codebook vector depending on the autocorrelation matrix R. The matrix determiner is configured to determine the autocorrelation matrix R by determining vector coefficients of a vector r, wherein the autocorrelation matrix R includes a plurality of rows and a plurality of columns, wherein the vector r indicates one of the columns or one of the rows of the autocorrelation matrix R, wherein R(i, j)=r(|i−j|), wherein R(i, j) indicates the coefficients of the autocorrelation matrix R, wherein i is a first index indicating one of a plurality of rows of the autocorrelation matrix R, and wherein j is a second index indicating one of the plurality of columns of the autocorrelation matrix R.
US11264034B2
A voice identification method, device, apparatus, and a storage medium are provided. The method includes: receiving voice data; and performing a voice identification on the voice data, to obtain first text data associated with the voice data; determining common text data in a preset fixed data table, wherein a similarity between a pronunciation of the determined common text data and a pronunciation of the first text data meets a preset condition, wherein the determined common text data is a voice identification result with an occurrence number larger than a first preset threshold; and replacing the first text data with the determined common text data.
US11264033B2
Methods, apparatus, systems, and computer-readable media are provided for storing incomplete dialog sessions between a user and an automated assistant in order that the dialog sessions can be completed in furtherance of certain actions. While interacting with an automated assistant, a user can become distracted and not complete the interaction to the point of the automated assistant performing some action. In response, the automated assistant can store the interaction as a dialog session. Subsequently, the user may express interest, directly or indirectly, in completing the dialog session, and the automated assistant can provide the user with a selectable element that, when selected, causes the dialog session to be reopened. The user can then continue the dialog session with the automated assistant in order that the originally intended action can be performed by the automated assistant.
US11264030B2
Systems, methods, and devices for outputting indications regarding voice-based interactions are described. A first speech-controlled device detects spoken audio corresponding to recipient information. The first device captures the audio and sends audio data corresponding to the captured audio to a server. The server determines a second speech-controlled device of the recipient and sends a signal to the recipient's second speech-controlled device representing a message is forthcoming. The recipient's second speech-controlled device outputs and indication representing a message is forthcoming.
US11264023B2
Input context for a statistical dialog manager may be provided. Upon receiving a spoken query from a user, the query may be categorized according to at least one context clue. The spoken query may then be converted to text according to a statistical dialog manager associated with the category of the query and a response to the spoken query may be provided to the user.
US11264016B2
The present disclosure relates to a noise manageable electronic device and a control method thereof as the disclosure capable of operating even in the Internet of Things (IoT) environment through a 5G communication network, and the electronic device of the present disclosure may control the driving of the electronic device that generates noise when a voice command is generated by a user. The present disclosure may be configured to include a receiver configured to receive the voice command from the user and noise generated from a plurality of electronic devices arranged in the home, a noise extractor configured to extract the noise, and a processor configured to determine whether the received voice command is recognizable, and to reduce the noise by controlling driving of a first electronic device that has generated the noise among the plurality of electronic devices, when it is determined that the voice command is not recognizable.
US11264009B2
A computer-implemented method for training a dialogue response generation system and the dialogue response generation system are provided. The method includes arranging a first multimodal encoder-decoder for the dialogue response generation or video description having a first input and a first output, wherein the first multimodal encoder-decoder has been pretrained by training audio-video datasets with training video description sentences, arranging a second multimodal encoder-decoder for dialog response generation having a second input and a second output, providing first audio-visual datasets with first corresponding video description sentences to the first input of the first multimodal encoder-decoder, wherein the first encoder-decoder generates first output values based on the first audio-visual datasets with the first corresponding description sentences, providing the first audio-visual datasets excluding the first corresponding video description sentences to the second multimodal encoder-decoder. In this case, the second multimodal encoder-decoder generates second output values based on the first audio-visual datasets without the first corresponding video description sentences.
US11264008B2
A method and an electronic device for translating a speech signal between a first language and a second language with minimized translation delay by translating fewer than all words of the speech signal according to a level of understanding of the second language by a user that receives the translation.
US11263993B2
In some embodiments, an upstream facing port device (UFP device) is connected to a DisplayPort source device via a connection that complies with the DisplayPort specifications. A downstream facing port device (DFP device) is connected to a DisplayPort sink device via a connection that complies with the DisplayPort specifications. The UFP device and the DFP device are connected via an extension medium to allow the DisplayPort source device to provide video and/or audio for presentation by the DisplayPort sink device. In some embodiments, the UFP device and/or the DFP device may be configured to provide video extracted from the DisplayPort communication to an external video processing device for processing before and/or after transmission over the extension medium.
US11263992B2
Display status agents executing on plural information handling systems coordinate presentation of visual images at plural displays by plural information handling systems through a display status memory external to the plural information handling systems, such as at a network location, a docking station or the displays. By referencing the display status memory, each display status agent determines information handling systems interfaced with each display and selects displays to present visual information based upon end user preferences to minimize manual interactions by an end user to accomplish a desired display presentation configuration.
US11263985B2
A power supply circuit and a display device are provided, belonging to the field of display technologies. The power supply circuit includes a boosting sub-circuit and a driving sub-circuit. The boosting sub-circuit may boost the voltage of the power signal provided by the power source; the driving sub-circuit may drive the load to work normally while ensuring that the capacitance of the capacitor in the driving sub-circuit is small when supplying power to the load with the power signal of which the voltage is boosted.
US11263984B2
An image signal processing device of the present disclosure includes a luminance correction section that performs, on a basis of information on a maximum output luminance value in a display section, luminance correction on an image signal to be supplied to the display section, the maximum output luminance value being variable.
US11263983B2
According to one embodiment, a display device includes a display panel on which a plurality of pixels having a light emitting element is disposed and a display control unit configured to display an image on the display panel by causing each of the plurality of pixels to emit light based on a pixel signal that defines luminance of each of the plurality of pixels. The display control unit is configured to display the image by decreasing luminance of a first pixel which is a protection target pixel of the plurality of pixels and increasing luminance of a second pixel disposed around the first pixel.
US11263982B2
A display having a variably controlled backlight and/or driver is disclosed. The backlight includes a first light source that emits light within a first spectral power distribution and has a first radiant power output. A second light source emits light within a second spectral power distribution matched to an optical filter for producing a perceived chromaticity and luminosity matching the perceived display appearance without the optical filter.
US11263941B2
Embodiments of the present disclosure relate to a data driving circuit, a driving method thereof, an array substrate, and a display panel. The data driving circuit includes a data driver, a multiplex circuit, and a control circuit. The data driver includes M data output terminals, and each of the data output terminals provides a data signal to L data lines via the multiplex circuit. The multiplex circuit includes M×L switch groups, and each of the switch groups includes N switch tubes and is coupled between one data line and the corresponding data output terminal. Each switch tube is coupled to one of L×N gate control terminals of the control circuit. Each gate control terminal is coupled to M switch tubes that are spaced apart from each other by (L×N×1) switch tubes. In the embodiments, M is an integer, and L and N are integers greater than or equal to 2.
US11263932B2
A display device includes a display panel which includes a display area which displays an image on a first major surface of the display panel. The display panel includes a first folding portion, a second folding portion, and a third folding portion which are disposed in the display area, and an extension direction of the first folding portion, an extension direction of the second folding portion, and an extension direction of the third folding portion are different from each other.
US11263930B2
A flexible display device is configured to be bendable along at least one bending axis, have two opposite sides at both ends of the bending axis, respectively, and include a first substrate and a second substrate opposite to each other, and a hetero-shaped double-sided adhesive tape bonding the first substrate and the second substrate to each other on at least one of the two opposite sides. The hetero-shaped double-sided adhesive tape includes a lower adhesive layer, a base material layer, and an upper adhesive layer which are stacked together in sequence. In a stacking direction of the lower adhesive layer, the base material layer and the upper adhesive layer, the upper adhesive layer has a non-overlapping region that does not overlap the lower adhesive layer, and/or the lower adhesive layer has a non-overlapping region that does not overlap the upper adhesive layer.
US11263913B2
Apparatuses, components, methods, and techniques for facilitating learning and managing an educational environment are provided. In an example, the system includes at least one processing device and at least one computer-readable storage device storing data instructions. The data instructions cause the at least one processing device to generate an online educational portal, the online educational portal including a student information system, a class scheduler engine and at least one of a presentation module, a searchable directory of curricular resources, and an analytics engine. The class scheduler engine is configured to generate class schedules. The presentation module operates to display information about various school entities. The analytics engine operates to evaluate relationships between activities users have engaged in and assessed skills of those users in various other activities.
US11263905B2
A system can receive a request for a service from the computing device of a given user of the network service. Based on the request, the system can determine a vehicle stopping location for a driver of a vehicle that is to service the request, and transmit map data to the computing device of the driver to present map content indicating (i) the vehicle stopping location for a vehicular portion of the service, and (ii) a path for the driver from the vehicle stopping location to a target location, the path to be followed by the driver upon parking the vehicle at the vehicle stopping location. The system can further transmit a set of delivery instructions to the computing device of the driver to specify one or more actions for delivering an item to the given user at a location specified by the given user.
US11263901B1
Traffic light phase timing effectiveness is determined. Connected vehicle data indicative of traffic conditions for one or more intersections is received. Factors from the connected vehicle data that are indicative of intersection performance are identified. The factors are weighted according to defined weights to determine an intersection score. Based on the score failing to meet one or more criteria, an alert to adjust intersection cycle is provided.
US11263895B2
An audio riser active electrical supervision system includes a high-voltage audio alert system connected to a riser circuit. The high-voltage audio alert system disconnects a high-voltage analog signal from the riser circuit when the audio riser active electrical supervision system operates in a standby mode, and connects the high-voltage analog signal to the riser circuit when the audio riser active electrical supervision system operates in an active alert mode. A plurality of isolator modules operate in a closed state that connects a circuit node to the riser circuit and an open state that disconnects the respective circuit node from the riser circuit. A riser supervision circuit is connected to at least one isolator module to detect a circuit fault on the riser circuit when the audio riser active electrical supervision system operates in the standby mode and the active alert mode.
US11263894B1
In an approach to 5G mobile device based regional patrolling over highways, a fifth generation (5G) mobile ad-hoc network is enabled based on data received from checkpoints. A 5G traffic channel is connected between the 5G mobile ad-hoc network and a virtual network function (VNF). Responsive to detecting that a vehicle containing a 5G UE device is in the ad-hoc network, a 5G traffic channel is connected between the UE device in the vehicle and the VNF. Responsive to receiving location information from the UE device in the vehicle, the location trajectory for the vehicle is determined. Responsive to determining that the location trajectory for the vehicle is improbable, a signal is sent to a patrol manager, where the signal includes a last received location for the vehicle.
US11263890B1
The vehicle occupancy reminder is configured for use with a vehicle that is further defined with a vehicle engine control unit (VECU) that generates an ignition off signal and a door open signal. The vehicle occupancy reminder monitors the vehicle for a passenger in a child safety seat. The vehicle occupancy reminder generates a plurality of alarms when: a) a passenger is detected in the child safety seat after the VECU has transmitted an ignition off signal to the vehicle occupancy reminder; or, b) a passenger is detected in the child safety seat after the VECU has transmitted a door open signal to the vehicle occupancy reminder. When the vehicle occupancy reminder detects a selected alarm condition alarm condition, the vehicle occupancy reminder generates a plurality of visual, audible, and tactile alarms that alert an appropriate authority that a selected alarm condition has occured.
US11263889B2
Systems, methods, and articles of manufacture provide for systemic resource utilization analysis and management, such as employing a single-point sensor to detect or identify resource leakage at one or more other locations in a structure.
US11263887B1
A health advisory alert system for a vehicle is presented. A controller may determine whether a vehicle occupant is preparing to exit the vehicle. Upon determination that the vehicle occupant is preparing to exit the vehicle, the controller may determine a location of the vehicle, determine a health advisory metric based on the location of the vehicle, and determine whether personal protective equipment should be worn based on the health advisory metric. Upon determination that personal protective equipment should be worn, the controller may output a notification to the vehicle occupant indicating that personal protective equipment should be worn.
US11263883B2
A system on a chip (SoC) for smoke detection includes power regulator circuits coupled to respective pins and analog sensor amplifier circuits that are each coupled to a respective pin of the pins coupled to the power regulator circuits. A first analog sensor amplifier circuit of the analog sensor amplifier circuits has a photoelectric amplifier circuit, a first LED driver and a second LED driver. The SoC also has a digital core that includes a digital logic circuit, register bits, and an MCU communication circuit. The MCU communication circuit is coupled to a data pin, the register bits are coupled to control or modify operation of the power regulator circuits and the analog sensor amplifier circuits, and the register bits are operable to be written to by an MCU.
US11263881B2
A method is provided. The method includes: establishing a database of a plurality of individuals, data for each individual including identity, short range wireless device information, and at least one rule regarding expected interaction by the individual relative to the area; receiving probe signal information from a plurality of sensors around an area, each of the sensors being configured to receive probe signals from proximate wireless devices, the probe signals lacking information directly identifying an owner of the originating wireless device; cross referencing at least some of the received probe signals with at least a portion of the database; identifying, based at least on the cross referencing, a presence of an unauthorized individual in the area; and notifying a supervising authority of the identified unauthorized individual.
US11263879B2
The apparatus and methods of the present invention provide improved accuracy of response for a tactile transducer included in a body-mounted device such as a headphone, VR/AR headset or similar device. Accuracy is increased through the application of digital signal processing, such as with Infinite Impulse Response filters or Finite Impulse Response filters.
US11263869B2
Near Field Communication (NFC) chips or tags are securely activated where at least one validation or redemption number is assigned to the chip or tag at the time of activation. Subsequent to activation, the NFC chip or tag enables secure data access via an Ancillary Device. Validation or redemption of the NFC chip or tag is also provided for.
US11263868B2
According to the present invention, there is provided a management system that prevents misuse of many game tokens during the operation of casino using card game tables in casino and other card game facilities using card game tables. The management system has a function that previously registers IDs of contemplated game tokens on database, manages IDs of game tokens present on a game table chip tray and a storage together with information on location on database, specifies the game token in the game table chip tray and the storage at predetermined timing, and generates an error signal when the following statuses is noticed: 1) a fact that ID absent on database is newly present and 2) a fact that two or more identical IDs are present.
US11263865B2
A gaming machine, system and method providing variable position display capable of display movement and an extendable screen responsive to gaming conditions. The gaming machine includes a cabinet, a variable position display, an extendable display screen, and a controller. The variable position display rotates, tilts, pans, or some combination of translation, rotation, tilting and panning, in relation to the cabinet and in response to at least one or more predefined gaming conditions. The controller initiates a movement sequence movement of the variable position display, from a first position to a second position, and initiates the game program tailored to retractably extend the extendable display screen with respect to the cabinet relatively to the movement of the variable position display, and present the game and game outcomes of the game on the variable position display in the second position.
US11263862B2
During play of a feature game, a gaming machine holds each feature trigger symbol at its respective display position, and if a column has spins remaining, spins/respins reels of the respective feature game column to obtain replacement symbols for each non-feature trigger symbol in the feature game column. For each of the feature game columns, the gaming machine determines, based on the symbols in the feature game column, whether to award a prize associated with the respective feature game column. Aspects of the feature game may be implemented in a base or primary game.
US11263859B2
A maintenance monitoring apparatus includes: a maintenance management part that manages, based on a monitoring result of a current or power of a vending machine that provides a beverage by extracting the beverage from a raw material, whether an operation performed on the vending machine is a predetermined maintenance operation and whether the maintenance has been executed at an appropriate time interval and as many times as necessary; and a notification part that notifies that a maintenance has been executed or not.
US11263858B2
A cash processing system capable of preventing erroneous operations by an operator during cash transfer processing and enabling the cash transfer to be executed efficiently. This system comprises a first cash processing machine for performing an outgoing cash transfer, a second cash processing machine for performing an incoming cash transfer, and a portable terminal. The portable terminal is equipped with a display unit, an operation unit for receiving input of cash transfer information, including cash information, and a communication processing unit. Upon receiving outgoing cash transfer information included in the cash transfer information from the portable terminal, the first cash processing machine pays out cash based on the outgoing cash transfer information. Upon receiving incoming cash transfer information included in the cash transfer information from the portable terminal, the second cash processing machine receives cash based on the incoming cash transfer information.
US11263835B2
A vehicle fault detection system including at least one sensor configured for coupling with a vehicle system, a vehicle control module coupled to the at least one sensor, and being configured to receive at least one time series of numerical sensor data from the at least one sensor, at least one of the at least one time series of numerical sensor data corresponds to a respective system parameter of the vehicle system being monitored, generate a graphical representation for the at least one time series of numerical sensor data to form an analysis image of at least one system parameter, and detect anomalous behavior of a component of the vehicle system based on the analysis image, and a user interface coupled to the vehicle control module, the user interface being configured to present to an operator an indication of the anomalous behavior for the component of the vehicle system.
US11263830B2
Among other things, a determination is made that intervention in an operation of one or more autonomous driving capabilities of a vehicle is appropriate. Based on the determination, a person is enabled to provide information for an intervention. The intervention is caused in the operation of the one or more autonomous driving capabilities of the vehicle.
US11263829B2
The present document provides image processing methods and apparatus. One claim recites: obtaining a signal to be encoded in color image data, the signal comprising a plural-bit payload; predicting a resulting color of overprinting several inks on a substrate, the overprinting representing the color image data encoded with the signal; using the resulting color for both i) visibility evaluation of the overprinting, and ii) signal robustness evaluation of the overprinting as seen by an imaging device. Other claims and combinations are provided.
US11263815B2
A system for adapting virtual reality (VR) or augmented reality (AR) content for learning based on a user's interests includes a personalization engine that determines a user's interests and knowledge level regarding a topic, a content modifier that modifies VR or AR content related to the topic according to the users interests and knowledge level, an object selector that selects VR and AR models used to teach the topic during a VR or AR session and modifies the VR and AR models with the modified content based on the user's interests and knowledge level; a VR engine that renders the modified VR and AR models into VR or AR images, and a VR display that displays the VR or AR images. The user's engagement is measured during interaction with the VR display and used to refine and improve an understanding of the user's interest and knowledge level regarding the topic.
US11263814B2
This application discloses methods and apparatus for rendering a virtual channel in a multi-world virtual scene. The method includes generating a virtual scene for displaying a virtual channel, a first world, and a second world, the virtual channel being used for a render camera to move between the first and second worlds; and receiving a control request for triggering the render camera to move in the virtual scene; and identifying a location of the render camera in response to the control request to obtain a movement trajectory of the render camera during movement in the virtual scene. The method further includes detecting a world state according to the movement trajectory; determining whether the world state is an intermediate state; in response to determining the world state is the intermediate state, generating a room for accommodating the render camera; and displaying in the virtual scene the room.
US11263813B2
Disclosed herein is an information processing device including an acquiring unit that acquires positional information of a flat surface present in a first space around a first user and positional information of a flat surface present in a second space around a second user, and a transformation parameter determining unit that determines a coordinate transformation parameter for transforming position coordinates of the first space and the second space into position coordinates in a virtual space such that a position of the flat surface present in the first space and a position of the flat surface present in the second space coincide with each other. A position of an object present in the first space and a position of another object present in the second space are transformed into positions in the virtual space according to the determined coordinate transformation parameter.
US11263809B2
A TBM-mounted virtual reconstruction system and method for a tunnel surrounding rock structure, the method including: obtaining image information of surrounding rock; receiving the image information of the surrounding rock; transforming and splicing pictures taken at different angles, to form a complete image reflecting the surrounding rock; recognizing and describing a surrounding rock feature of the complete image, and transmitting the annotated image to a virtual reconstruction module; displaying the complete image with a description of the surrounding rock feature by using a virtual reality device, to reflect surrounding rock situations at different angles/different positions. This has the advantages of high equipment automation, not prolonging the construction time, not requiring the sketcher to enter the tunnel, precise surrounding rock feature parameters, and supporting remote control.
US11263800B2
Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.
US11263795B1
Described are systems and techniques to generate data for display to present visualizations of data acquired from sensors in a facility. The data visualizations may be used to develop, configure, administer, or otherwise support operation of the facility. In one implementation, the visualization may include a view incorporating aggregated images acquired from multiple cameras, depth data, tracking information about objects in the facility, and so forth. An analyst may use the data visualization to determine occurrence of an action in the facility such as a pick of an item, place of an item, what item was involved with an action, what user was involved with the action, and so forth. Based on the information presented by the data visualization, changes may be made to data processing parameters.
US11263794B2
Disclosed are a binocular see-through AR head-mounted device and an information displaying method thereof. Sight mapping relationship η is preset in the head-mounted device, human eye spatial sight information data of a user is tracked and calculated by a sight tracking system, virtual information that needs to be displayed is displayed on the left and right lines of sight of the human eyes on the basis of a binocular see-through AR head-mounted device virtual image imaging principle and a human eye binocular vision principle, thus implementing accurate overlap of the virtual information to the proximity of the position of the fixation point of the human eyes, allowing a high degree of integration of the virtual information with the environment, and implementing enhanced virtual reality in the true sense. The present invention provides a simple solution, requires only the sight tracking system to complete the process, obviates the need for excessive hardware facilities, and is inexpensive.
US11263789B2
Disclosed is an image processing apparatus and a method of operating the same. The image processing apparatus includes: a memory storing information on at least one random patch; and at least one processor configured to: obtain correlations between a pixel block included in an input image and each of a plurality of random patches obtained from the information on the at least one random patch, obtain weights respectively for the plurality of random patches on a basis of the obtained correlations and apply the weights respectively to the plurality of random patches, and obtain an output image by applying, to the pixel block, the plurality of random patches to which the weights are respectively applied.
US11263786B2
When decoding a data array that has been encoded using a tree structure representation, the encoded tree representation of the array of data elements comprising a set of tree node data representing the respective node values for the different nodes of the tree and a set of bit count data indicating the number of bits that has been used for signalling the node values for each non-root node in the tree a data value for a set of one or more data elements associated with a first node of the tree structure is determined by determining an initial data value for the first node using the stored tree node data, and modifying the initial data value using a modifier value based on the number of bits used for signalling the node values for the child nodes of the first node in at least the next level of the tree.
US11263779B2
In an example, an apparatus includes a first sensor, a second sensor, and a controller. The first sensor collects a first set of data describing a three-dimensional object that is placed in a constant position in a scene. The second sensor collects a second set of data describing the three-dimensional object. The first sensor has a first position in the scene, while the second sensor has a second position in the scene. The controller generates a first rendering of the three-dimensional object from the first set of data and generates a second rendering of the three-dimensional object from the second set of data. The controller also determines the first position and the second position based on an alignment of the first rendering and the second rendering with a three-dimensional model of the three-dimensional object.
US11263776B2
An object recognition system using an ultrasonic sensor is proposed, the system including an amplifier amplifying an output of the ultrasonic sensor; an analog-to-digital converter converting an output of the amplifier into a digital signal; and a feature point extractor extracting feature points using an output of the analog-to-digital converter; and an object recognizer recognizing the object by using the feature points extracted from the feature point extractor.
US11263759B2
In an image processing apparatus, a detection unit detects a moving object from a captured image captured by an image capturing unit. An extraction unit extracts an edge from the captured image. A determination unit determines, based on a position of the moving object included in the captured image, whether to superimpose the edge on a region corresponding to the moving object in a background image. A generation unit generates an output image by superimposing a mask image, for obscuring the moving object, on the region in the background image and superimposing the edge, determined by the determination unit to be superimposed, on the region in the background image.
US11263758B2
The present disclosure relates to a controller (2) for identifying a periphery of a towed vehicle (T) connected to a towing vehicle (V). The controller (2) is configured to receive towing vehicle image data (DV1) corresponding to a towing vehicle image (IMG1) captured by a towing vehicle camera (C1). The towing vehicle image data (DV1) is processed to generate a plurality of movement vector. The periphery (P1) of the towed vehicle (T) is identified in dependence on the plurality of movement vectors. The present disclosure also relates to a method of identifying the periphery (P1) of a towed vehicle (T).
US11263755B2
The present disclosure provides an alert device and an alert method. The alert device includes an image capturing unit, an input/output unit and a processing unit. The image capturing unit is configured to capture at least one image of a wafer transportation system. The processing unit is configured to: retrieve the at least one image from the image capturing unit; define a first boundary in the at least one image; identify a wafer chuck of the wafer transportation system in the at least one image; determine whether the wafer chuck intersects the first boundary in the at least one image; and transmit an alert signal to the wafer transportation system via the input/output unit when the wafer chuck is determined to intersect the first boundary in the at least one image.
US11263754B2
Methods, systems, and non-transitory machine-readable storage medium for volumetric segmentation of structures in planar medical images. The method includes, for example, receiving a plurality of planar medical images including a structure and displaying a first planar medical image. The method also includes determining and displaying a first two dimensional (2D) contour of the structure using a first single straight line segment between user-selected first and third locations in the first planar medical image. The method further includes determining and displaying a second 2D contour of the structure using a second single straight line segment between user-selected first and second locations in the first planar medical image. The method also includes determining a three dimensional (3D) contour of the structure using the second single straight line segment. The method further includes determining a long axis of the structure using the 3D contour and outputting a dimension of the long axis.
US11263735B2
A system and method for constructing a digital composite image of a three-dimensional biological sample. The system includes an optical system that captures images of cells and tissue presented on a specimen slide. The system systematically acquires a stack of images at different segments across the specimen slide. For each segment, the system dynamically calculates an optimal focal plane. Once an optimal focal plane is determined for each of the stacks of images, the system generates a composite image by copying the sharpest objects from each of the optimal focal planes.
US11263734B2
An electronic device, a method and a storage medium are disclosed. The electronic device includes a processor and a memory operatively coupled to the processor. The processor is configured to receive a user input from an external electronic device. The processor is also configured to synthesize a first region that is a first partial region of a first raw image and a second partial region of a second raw image based on the user input to generate a composite raw image. The processor is further configured to modify at least one of a first attribute of the first raw image and a second attribute of the second raw image to generate a third attribute. Additionally, the processor is configured to calibrate the composite raw image using the third attribute to generate a composite image.
US11263730B2
An image processing method determining a format of first image data, determining a first interface mode that is currently used, where the first interface mode is determined when the processing device establishes physical connections with a display device, and the format of the first image data format is not supported by the first interface mode, and processing, the first image data based on the first interface mode to generate second image data, where a format of the second image data is supported by the first interface mode. Image data will be processed when an image format of the image data is not supported by the first interface mode.
US11263727B2
Provided is an image enhancement method, performed by a data processing device, the method including: performing a first edge-preserving filtering on an original image to obtain a first processed image; obtaining a detail feature of the original image based on the original image and the first processed image; determining a second processed image according to the detail feature and the first processed image; and processing the second processed image in a guided image filtering manner by using the original image as a first guidance image, to obtain a third processed image, and outputting the third processed image to be displayed.
US11263725B2
An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
US11263719B2
Aspects described herein are directed to leveraging multiple graphics processors, by a virtual GPU manager, to optimize the rendering of graphics in either a desktop or virtual desktop environment. The virtual GPU manager may enumerate all available physical GPUs, query performance variables including processing capacity of each of the available physical GPUs, and classify each of the physical GPUs based on the queried performance variables. Further, the virtual GPU manager may generate a logical GPU corresponding to one or more of the available physical GPUs. The virtual GPU manager may distribute graphics rendering requests across each of the plurality of available physical GPUs by way of the logical GPU.
US11263718B2
A method for graphics processing. The method including rendering graphics for an application using a plurality of graphics processing units (GPUs). The method including dividing responsibility for the rendering of geometry of the graphics between the plurality of GPUs based on a plurality of screen regions that are interleaved, each GPU having a corresponding division of the responsibility which is known to the plurality of GPUs. The method including assigning a GPU a piece of geometry of an image frame generated by an application for geometry pretesting. The method including performing geometry pretesting at the GPU to generate information regarding the piece of geometry and its relation to each of the plurality of screen regions. The method including using the information at each of the plurality of GPUs when rendering the image frame.
US11263712B2
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for computerized travel services. One of the methods includes identifying photographs using an index of photographs, the photographs being identified from the index as photographs geographically related to a point of interest or destination and having a creation timestamp corresponding to a time of the year; determining for each of the photographs, a relevancy score based at least in part on: selection success data of the photograph for image queries referring to the point of interest or destination, and references to the point of interest or destination in documents associated with the photograph; and selecting a selected photograph from the photographs based at least in part on a respective visual quality score and the respective relevancy scores, the visual quality score representing a degree of visual quality of the respective photographs.
US11263700B1
Aspects of the invention are directed to methods and systems for efficiently communicating data between an insurer and a non-referral repair shop, e.g., vehicle repair shops that are normally not preapproved by the insurer to perform the estimating and repair work. The methods and systems described herein are particularly useful for insurers utilizing non-referral repair shops for servicing vehicles involved in insurance claims. According to aspects of this invention, the insured may be able to select a non-referral repair shop, not delegated or preapproved by the insurer, thereby generally allowing the insured to select any available vehicle repair shop.
US11263698B1
System, apparatuses, computer-implemented methods, and computer-readable media executable by insurance system servers and user computing devices for receiving requests for insurance products are provided. In order to determine one or more factors of the insurance product or policy, the system may use body characteristics of the customer or potential customer, such as height, weight, body mass index, and the like. In some examples, this information may be determined from one or more images provided by the user. For instance, one or more images of the customer or potential customer may be captured and transmitted to the system for processing. Based on the received images, the system may determine various body characteristics of the user and may use that information to determine one or more policy factors for the insurance product or policy, such as premium, coverage, term, type of policy, or the like.
US11263697B2
Various aspects of the subject technology relate to systems, methods, and machine-readable media for investigating an insurance claim. A system may be configured to perform operations including establishing a video conferencing session with a mobile device associated with an insurance product and providing a user interface configured to provide a claims adjuster with remote control of a set of functions on the mobile device associated with the insurance product during the video conferencing session. The operations further include receiving, via the user interface, instructions for requesting the mobile device to perform at least one function in the set of functions on the mobile device and transmitting, to the mobile device, a request to perform the at least one function on the mobile device.
US11263696B2
Screening of entities using multi-level rules and tolerances against entity data. The entity data are screened for multiple entities, including determining if the entity data comply with business activity rules. If a respective entity fails to comply with the business activity rules, investments with the non-compliant entity are added to a list of non-usable investments. If the respective entity complies with the business activity rules, the respective entity is identified as a business-activity-compliant entity. Each respective business-activity-compliant entity is then screened using multiple screening methodologies, which are applied to screen the entity data for the respective business-activity-compliant entity against each of the financial rules in accordance with the respective screening methodology. If the financial rules satisfy at least one tolerance setting, investments with the respective business-activity-compliant entity are added to a list of usable investments; otherwise, investments with the respective business-activity-compliant entity are added to the list of non-usable investments.
US11263695B2
Systems and methods are disclosed herein that compute trading signals with low latency and high throughput using highly parallelized compute resources such as integrated circuits, reconfigurable logic devices, graphics processor units (GPUs), multi-core general purpose processors, and/or chip multi-processors (CMPs). Examples of trading signals that can be computed in this fashion include a liquidity indicator that indicates a presence of a reserve order for a financial instrument, a liquidity estimation that estimates an amount of hidden liquidity for a financial instrument, a quote price stability estimation that estimates a duration of time for which a price quote for a financial instrument will be valid, and/or a quote price direction estimation that estimates whether the price in a next quote for a financial instrument will be higher or lower than the price for that financial instrument in the current quote.
US11263694B2
A method to assist in the operation of a financial market. The method including receiving one or more transaction messages, where the one or more transaction messages include one or more orders or order commitments to be executed on the financial market; imposing one or more delays on the one or more orders or order commitments using a delay algorithm; processing the one or more order or order commitments by opening the one or more transaction messages after the one or more delays; matching the opened orders or order commitments; and executing the matched orders or order commitments.
US11263690B2
A location associated with an on-demand electric vehicle is determined dynamically during a ride to be associated with one or more restrictions. Configuration data is used to enforce the one or more restrictions with respect to operation of the on-demand electric vehicle in connection with the ride.
US11263686B2
A network node associated with a retail store maintains personalized purchasing information identifying one or more products purchased by a customer. Each product is associated with one or more preference tags identifying a respective product category for the product, and indicating the customer's preference for products in that product category. Based on this information, the network node recommends products for the customer to purchase, and indicates those recommendations by controlling the customer's wireless device to visually indicate the location of the recommended products in the store.
US11263685B1
Disclosed are various embodiments for identifying complementary items to items available for sale, lease, download, rent, etc. by different merchants in an electronic commerce system and presenting the complementary items alongside requested items in a user interface to improve a user experience when interacting with the electronic commerce system. The user interface includes a first user interface object that includes the requested items and a second user interface object that includes the complementary items to the requested items. The complementary items are displayed in the second user interface object in vertical alignment with a position of the corresponding requested item in the first user interface object.
US11263680B2
Disclosed is a non-transitory computer readable medium storing a computer program. The computer program performs operations for analyzing a video when the computer program is executed by one or more processors of a computing device and the operations may include: separating contents into one or more subcontents by analyzing the contents; matching and storing additional information with the subcontents; receiving search information from a user terminal; and sending at least one of the contents, the subcontents or the matched additional information corresponding to the search information to the user terminal.
US11263675B2
A method of a buyer and a seller information network sharing service is provided. The method includes providing information from a seller of at least one product to a potential buyer. The buyer is able to request a meeting to inspect the product, either a car, home, or consumer product. The seller upon accepting a meeting request, has an application on a mobile device that will access real-time location data for display on the seller mobile device to provide an estimated time of arrival of the buyer, to the seller location.
US11263673B2
A purchase information utilization system according to the present invention includes a system provided with a reception unit that receives purchase information including identification information capable of identifying a product and support information which supports that the product is purchased from a terminal device of a consumer, a purchase information storage unit that stores the purchase information received by the reception unit, and a determination unit that determines whether or not the consumer has purchased the product using the support information included in the purchase information received by the reception unit.
US11263671B2
A method of providing an ad extension includes selecting an advertisement for display. The method also includes selecting additional information related to the advertisement. The method also includes transmitting data representing the advertisement to a browser. The browser interacts with an expandable API to render an inline frame having an advertisement slot. The browser renders and displays the advertisement in the frame. The method also includes transmitting display data representing the additional information related to the advertisement to the browser. The browser receives an input to activate the ad extension. In response to the input, the browser interacts with the expandable API system to expand and render the frame. The browser renders, in the frame, the advertisement slot containing the advertisement. The browser also renders, in the frame, the additional information. The browser displays the expanded inline frame, such that the displayed frame covers a portion of the content.
US11263670B2
The disclosed systems and methods integrate gaming functionality with viewing a video program. Systems and methods for generating an interactive multimedia game for a user during the viewing of a video program by the user includes a host computer that generates the game in a context of the video program viewed on a first graphical user interface and recommends the video game to the user. The user may opt to engage with the video game on a second graphical user interface, which may be overlaid on the first graphical user interface.
US11263659B2
A promotion program analytical system and method is disclosed. The promotion program analytical system and method selects a promotion program to offer to a consumer. Selection of the promotion program to present to the consumer includes determining a probability that the consumer will accept the promotion program. The probability of acceptance may be determined based on past performance data of similar promotion programs, and also past performance data on the promotion program itself when it is available.
US11263652B2
A non-transitory computer-readable medium storing a game program for a game which is played through a network causes a computer to realize a selection receiving function of receiving, from one user, the selection of whether to transmit a message to other user, an extraction function of extracting at least one other user to which the message is transmitted, on the basis of a certain condition, a message transmitting function of transmitting the message to the at least one other user extracted by the extraction function when the selection receiving function receives the selection indicating that the message is transmitted to the other user, and a reward giving function of giving a reward to the one user when the message transmitting function transmits the message to the at least one other user extracted by the extraction function.
US11263651B2
A server device determines a first item number by specifying a first object correlated with an item number of items defined in a game and determines a change value by specifying a second object correlated with the change value for changing the first item number. The server device changes the first item number to a second item number on the basis of the determined first item number and the determined change value and gives a reward on the basis of the second item number.
US11263647B2
Disclosed herein is a method for managing customer relationship through multiplex-assigning password of access point. According to an exemplary embodiment of the present invention, a method for managing a customer relationship by a customer management server includes: receiving customer terminal information including customer terminal identification information and customer group identification information within a shop being transmitted by accessing the access points of a plurality of customer terminals; and setting the plurality of accessed customer terminals as the same group in customer groups within the same shop based on the received customer group identification information within a shop and storing the set group in customer information corresponding to the customer terminals included in the group as customer social information.
US11263644B2
In a method for detecting unauthorized or suspicious financial activity, a graph convolutional network for financial crime prevention, a separate node is created for each entity: each account, each person, each address (e.g. email address), etc. Separate attributes are provided to aggregate transactions in which the node acts as a sender; transactions in which the node acts as a receiver; transactions using a specific channel (e.g. ATM); and transactions of a specific type (e.g. online money transfer). In some embodiments, the attributes exclude data on individual transactions to reduce the amount of data and hence provide more effective computer utilization. The approach is suitable for many applications, including anti-money laundering. Other features are also provided, as well as systems for such detection.
US11263641B2
Providing a cognitive blockchain for user privileges is provided. A distributed secure encrypted ledger is established for storing information related to privileges for users across a plurality of nodes in a permissioned network with known identities. An internet of things (IoT) device node in the plurality of nodes records a first block in the distributed secure encrypted ledger containing activity information related to a privilege corresponding to a user of the IoT device node. A licensing node in the plurality of nodes evaluates information in the first block. The licensing node records a second block containing privilege information corresponding to the user of the IoT device node based on the evaluating.
US11263637B2
A registration apparatus for registering commodity information includes a bar code reader configured to read commodity information from a symbol attached to a commodity, a wireless tag reader configured to read tag information stored in a wireless tag attached to a commodity, a first cancel key, and a processor configured to upon reading of tag information stored in a wireless tag via the wireless tag reader, acquire commodity information associated with the tag information and register the acquired commodity information as first data, upon reading of commodity information from a symbol via the bar code reader, register the read commodity information as second data, and upon detection of the first cancel key being operated, cancel registration of the commodity information registered as the first data.
US11263636B2
A method for providing a gift includes receiving a gift token creation request representative of a selection of a gift recipient and gift limitations from a first computing device. The method includes generating a tokenized PAN associated with a gift account and transmitting the tokenized PAN and gift limitations to a second computing device. The method includes detecting a transaction authorization request that is representative of an attempted transaction at a merchant POS device based on monitoring of transaction authorization data originating from a plurality of merchant POS devices. The transaction authorization request represents an attempted tokenized PAN, an attempted transaction amount and a merchant code. The method includes determining that the attempted tokenized PAN matches the tokenized PAN associated with the gift account. The method includes transmitting an authorization message to the merchant POS in response to determining that the transaction authorization request satisfies the gift limitations.
US11263628B2
Techniques are provided for fallback authorization routing. A merchant processor may receive authorization requests from one or more merchant systems. These authorization requests may be to authorize a transaction. The merchant processor may transmit these authorization requests over a first communication channel to an acquirer processor, which may then forward the requests to a payment network. If the merchant processor determines that the acquirer processor is not receiving the authorization requests, or is otherwise unavailable, the merchant processor may, as a fallback, transmit the authorization requests directly to the payment network through a second communication channel, thereby bypassing the acquirer processor. When the merchant processor receives some indication that the acquirer processor is available to process authorization requests, new authorization requests can be transmitted to the acquirer processor via the first communication channel.
US11263611B2
A computing system can receive a primary authorization request corresponding to use of a prepaid payment means of a user of the transaction service for a transaction with a merchant. Based on receiving the primary authorization request, that system can determine that an account balance corresponding to the prepaid payment means comprises inadequate funds to fulfill the transaction. In response, the system can automatically transmit a secondary authorization request to a financial entity associated with an account of the user, and subsequently receive an approval of the secondary authorization request, which enables the system to utilize the account of the user to make up for the inadequate funds of the account balance of the prepaid payment means. Based on receiving the approval, the system can transmit an authorization to the point-of-sale terminal of the merchant to authorize the primary authorization request for the transaction.
US11263608B2
Computer-readable media, methods, and apparatuses are disclosed for voucher management for attraction access. The computer-readable medium includes instructions stored thereon, which when executed on a processor, perform steps of receiving, from an attraction verification terminal for an attraction site, an access request for a customer presenting an access identifier. The instructions are also configured to retrieve, from a voucher engine, an attraction voucher based on the access identifier, and determine whether the attraction voucher has previously been validated. The instructions are also configured to construct access privilege data based on the attraction voucher. Upon a positive determination of a validation flag for the access privilege data, the instructions are also configured to construct and transmit, to the attraction verification terminal, a virtual access token permitting the access request for the customer to access the attraction site.
US11263604B2
Systems and methods are provided for processing credit token and debit token based transactions in a blockchain supported network.
US11263603B1
In one embodiment, a method includes identifying, by a payment service, a plurality of security assets for inclusion in a pack of security assets. A value of the pack of security assets may be determined based on weighted values of a base unit of each of the security assets. Information may be sent to a first user's client device to display a user interface to purchase the pack of security assets. In response to receiving a purchase request in a specified amount, the payment service may calculate, for each of the security assets in the pack, the base units of the security asset based on the respective assigned weight and the value of a base unit of the security asset. Finally, for each of the security assets in the pack, ownership of the calculated number of base units of the security asset may be assigned to the first user.
US11263586B2
A mobile Quality Management/Control system for performing mobile product inspections is provided. A mobile device, such as a tablet, is configured to communicate with one or more databases and allow for real time entry (and subsequent access) of the details of product inspections for quality control and management purposes. The details of such inspections are maintained and available for all subsequent inspections. The mobile device is further configured to provide inspectors with inspection procedures and/or tutorials associated with the inspections being performed.
US11263583B1
Load cells measure the weight of items on a shelf. Weight changes occur as items are picked from or placed to the fixture. Information about these weight changes is used to determine an estimated location on the shelf of a weight change. Hypotheses are generated using information about where particular types of items are stowed, the weights of those particular types of items, information about the weight changes, and the estimated locations of the weight changes. A model is used to produce confidence values in the hypotheses based on a change in weight measured at a first side and a change in weight measured at a second side of the shelf. A hypothesis with a confidence value that exceeds the threshold may be selected and used to determine interaction data indicative of a quantity picked or placed, type of item, and location on the shelf.
US11263569B2
The present specification discloses blockchain-based information processing methods, apparatus, and devices. The blockchain-based information processing method includes: obtaining tree-structured data describing target relationships from a blockchain; obtaining service data of a ith-level target in the tree-structured data describing target relationships from the blockchain, where i is a positive integer; and executing a smart contract used for resource allocation, to allocate resources to each ith-level target based on a resource allocation scheme that is in the smart contract and that corresponds to the service data of each of the one or more ith-level targets.
US11263558B2
A method for monitoring access to an electronically controllable device includes establishing communication between a mobile device and a control platform via a communication network. A booking, including first and second data, is created for a controllable device in the platform. The first data is access information and the second data is encrypted with an individual key which is assigned to an access control unit in the controllable device. The mobile device is wirelessly connected to the access unit and the second data, as well as a subset of the first data, is transmitted to the access unit which decrypts the second data and checks its signature. If the check is successful, a configuration of the access unit is adapted as a function of the decrypted data. Authorization for access to the controllable device by the mobile device is checked as a function of the decrypted data.
US11263550B2
A method and system of mitigating bias in a decision-making system are provided. A presence of bias is identified in one or more machine learning models. For each of the machine learning models, a presence of bias in an output of the model is determined. One or more options to mitigate a system bias during a processing stage, based on the identified presence of bias for each of the one or more models, are determined. One or more options to mitigate the system bias during a post-processing stage, based on the identified presence of bias in each output of the models, are determined. A combination of options is provided, including (i) a processing option for the processing stage, and (ii) a post-processing option for the post-processing stage, wherein the combination of options accommodates a threshold bias limit to the system bias and a total bias mitigation cost threshold.
US11263547B2
Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.
US11263546B2
Techniques are described in which a qubit is far off-resonantly, or dispersively, coupled to a quantum mechanical oscillator. In particular, a dispersive coupling between a physical qubit and a quantum mechanical oscillator may be selected such that control of the combined qubit-oscillator system can be realized. The physical qubit may be driven with an electromagnetic pulse (e.g., a microwave pulse) and the quantum mechanical oscillator simultaneously driven with another electromagnetic pulse, the combination of which results in a change in state of the qubit-oscillator system.
US11263543B2
A method includes identifying a graph of a social network, the graph including nodes and edges, each edge connects two nodes, some of the plurality of nodes represent members of the social network, some edges of the plurality of edges represent a relationship between two associated nodes, creating a first taste profile for a first member node, the taste profile identifying a first entity of interest to the first member, identifying a second member node based on an absence of a second taste profile for the second member node, the second member node is connected to the first member node, determining that the second member node is connected to the first member node, creating a second taste profile for the second member node using the first taste profile, and providing a recommendation to a member associated with the second member node based on the created second taste profile.
US11263541B2
Systems and methods are disclosed to build and execute a decision system based on multiple machine learned decision models. In embodiments, the decision system performs a hashing technique to reduce relevant features of the input data into a feature vector for each decision model. The feature vector reduces the dimensionality of the feature universe of the input data, and its use allows the decision models to be trained and executed using less computing resources. In embodiments, the decision system implements an ensembled decision model that makes decisions based on a combination function that combines the decision results of the individual models in the ensemble. The decision models employ different hashing techniques to hash the input features differently, so that errors caused by the feature hashing of individual models are reduced in the aggregate.
US11263539B2
A method and system for distributed machine learning and model training are disclosed. In particular, a finite asynchronous parallel training scheme is described. The finite asynchronous parallel training takes advantage of the benefits of both asynchronous parallel training and synchronous parallel training. The computation delays in various distributed computation nodes are further considered when training parameter are updated during each round of iterative training. The disclosed method and system facilities increase of model training speed and efficiency.
US11263534B1
A system and method that produces an accurate probability distribution representative of a target molecule that may be used in pharmacokinetics and analogous applications. A generator is seeded from a variational autoencoder during training and is then used after training in series with a second variational autoencoder to produce the probability distributions from molecular tensors.
US11263525B2
A neural network learns a particular task by being shown many examples. In one scenario, a neural network may be trained to label an image, such as cat, dog, bicycle, chair, etc. In other scenario, a neural network may be trained to remove noise from videos or identify specific objects within images, such as human faces, bicycles, etc. Rather than training a complex neural network having a predetermined topology of features and interconnections between the features to learn the task, the topology of the neural network is modified as the neural network is trained for the task, eventually evolving to match the predetermined topology of the complex neural network. In the beginning the neural network learns large-scale details for the task (bicycles have two wheels) and later, as the neural network becomes more complex, learns smaller details (the wheels have spokes).
US11263524B2
Embodiments described herein cover a hierarchical machine learning system with a separated perception subsystem (that includes a hierarchy of nodes having at least a first layer and a second layer) and application subsystem. In one example embodiment a first node in the first layer processes a first input and processes at least a portion of the first input to generate a first feature vector. A second node in the second layer processes a second input comprising at least a portion of the first feature vector to generate a second feature vector. The first node generates a first sparse feature vector from the first feature vector and/or the second node generates a second sparse feature vector from the second feature vector. A third node of the perception subsystem then processes at least one of the first sparse feature vector or the second sparse feature vector to determine an output.
US11263519B2
A method for unsupervised learning of a multilevel hierarchical network of artificial neurons wherein each neuron is interconnected with artificial synapses to neurons of a lower hierarchical level and to neurons of an upper hierarchical level. The method includes at a neuron the steps of integrating inference spikes from the interconnected neurons of the lower hierarchical level both in a first and a second accumulators using the same synaptic weights; when the first accumulator reaches a first threshold, generating a learning spike, resetting the first accumulator, triggering synaptic conductance modification in accordance with a spike-timing dependent plasticity rule and delivering the learning spike as an inhibitory signal to other neurons in the same hierarchical level; when the second accumulator reaches a second threshold, generating an inference spike, delivering the generated inference spike to the interconnected neurons of the upper hierarchical level, resetting the second accumulator and possibly delivering the inference spike as an inhibitory signal to other neurons in the same hierarchical level.
US11263512B2
A novel and useful neural network (NN) processing core adapted to implement artificial neural networks (ANNs) and incorporating strictly separate control and data planes. The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level. Dynamic resource assignment agility is provided which can be adjusted as required depending on resource availability and capacity of the device.
US11263511B2
A neural network training device according to an exemplary aspect of the present invention includes: a memory that stores a set of instructions; and at least one central processing unit (CPU) configured to execute the set of instructions to: determine a regularization strength for each layer, based on an initialized network; and train a network, based on the initialized network and the determined regularization strength, wherein the at least one CPU is further configured to determine the regularization strength in such a way that a difference between magnitude of a parameter update amount calculated from a loss function and magnitude of a parameter update amount calculated from a regularization term falls within a predetermined range.
US11263505B2
In some embodiments, a smart card may include a substrate with a first side and a second side. A first protective layer covers the first side and a second protective layer covers the second side of the substrate. Circuitry held in the substrate includes electronic interconnects for interconnecting circuitry elements. The circuitry elements include a processor, power circuitry for powering the circuitry elements, and an environmental detection sensor for respectively detecting a predetermined environmental parameter. The processor is configured to receive an output from the environmental detection sensor, to determine from the output that the environmental detection sensor detected an environmental alert trigger condition, and to generate an alert that is representative of the environmental alert trigger condition. The protective layers include pores in a region proximate to the environmental detection sensor for exposing the environmental detection sensor to an environment around the smart card.
US11263499B2
Technology disclosed herein may involve a computing system that (i) generates (a) a first feature map based on a first visual input from a first perspective of a scene utilizing at least one first neural network and (b) a second feature map based on a second visual input from a second, different perspective of the scene utilizing at least one second neural network, where the first perspective and the second perspective share a common dimension, (ii) based on the first feature map and a portion of the second feature map corresponding to the common dimension, generates cross-referenced data for the first visual input, (iii) based on the second feature map and a portion of the first feature map corresponding to the common dimension, generates cross-referenced data for the second visual input, and (iv) based on the cross-referenced data, performs object detection on the scene.