-
公开(公告)号:US20250070520A1
公开(公告)日:2025-02-27
申请号:US18945586
申请日:2024-11-13
Applicant: Molex, LLC
Inventor: Victor Zaderej , Alan Han , Richard Fitzpatrick
IPC: H01R13/66 , H01R13/52 , H01R43/20 , H01R43/24 , H05K1/14 , H05K1/18 , H05K3/00 , H05K3/34 , H05K3/36
Abstract: In an embodiment, a smart connector includes an Application Specific Electronics Packaging device formed by an Application Specific Electronic Packaging manufacturing process, and a separate printed circuit board electrically connected to electrical components of the Application Specific Electronic Packaging device. The ASEP Application Specific Electronic Packaging manufacturing process includes forming a continuous carrier web having a plurality of lead frames, overmolding a substrate onto the fingers of each lead frame, each substrate having a plurality of openings which exposes a portion of the fingers, electroplating the traces, and electrically attaching at least one electrical component to the traces to form a plurality of Application Specific Electronic Packaging devices. In some embodiments, the printed circuit board has electrical components configured to control the functionality of the electrical components. In some embodiments, the printed circuit board has electrical components configured to modify properties of the smart connector.
-
公开(公告)号:US20250063670A1
公开(公告)日:2025-02-20
申请号:US18939692
申请日:2024-11-07
Applicant: Aptiv Technologies AG
Inventor: David G. Siegfried , David R. Peterson , Joseph Sudik, JR.
Abstract: A system and method for shaping a flexible circuit (FC) having a set of conductive traces disposed within a set of insulation layers and a shaped FC, each involve using a non-conductive tool defining complimentary first and second tool portions and a shape therebetween, the tool being configured to receive a portion of the FC therebetween the first and second tool portions, a set of conductive heating elements arranged substantially in parallel with each other and disposed within the first and second tool portions, and a power source configured to provide power to the conductive heating elements causing the conductive heating elements to generate heat energy to shape the FC portion without removing any of the FC portion.
-
公开(公告)号:US20250063651A1
公开(公告)日:2025-02-20
申请号:US18725297
申请日:2022-12-21
Inventor: Kazuhiro MIYATA , Koji NITTA , Shoichiro SAKAI , Satoshi KIYA
Abstract: A printed wiring board includes: a dielectric layer having a main surface; and a conductive pattern. The conductive pattern includes a metal layer that is disposed on the main surface, an electroless plating layer that is disposed on the metal layer, and an electrolytic plating layer that is disposed on the electroless plating layer. An average thickness of the metal layer is 2.1 μm or more and 9.0 μm or less. Maximum height roughness of a surface of the metal layer opposed to the main surface is 5.0 μm or less.
-
公开(公告)号:US20250060329A1
公开(公告)日:2025-02-20
申请号:US18818879
申请日:2024-08-29
Applicant: Carnegie Mellon University
Inventor: Rahul Panat , Eric A. Yttri , Mohammad Sadeq Saleh
IPC: G01N27/327 , A61B5/24 , B33Y10/00 , B33Y70/10 , B33Y80/00 , C09D11/52 , G01N27/30 , H05K3/00 , H05K3/12
Abstract: A high-density bioprobe array is provided comprising conductive or optical shanks. A method of making high-density bioprobe arrays also is provided. A bioprobe system using the array also is provided.
-
公开(公告)号:US12232268B2
公开(公告)日:2025-02-18
申请号:US17680369
申请日:2022-02-25
Applicant: IBIDEN CO., LTD.
Inventor: Hirotaka Taniguchi , Akihide Ishihara
Abstract: A wiring substrate includes an insulating layer, and a build-up part formed on the insulating layer and including an interlayer insulating layer and a conductor layer. The build-up part has a cavity penetrating through the build-up part such that the cavity is formed to accommodate an electronic component and has an inner wall and a bottom surface having a groove and that the groove is extending entirely in an outer edge part of the bottom surface and formed continuously from the inner wall surface of the cavity.
-
公开(公告)号:US12232254B2
公开(公告)日:2025-02-18
申请号:US17879920
申请日:2022-08-03
Applicant: Unimicron Technology Corporation
Inventor: Po-Hsiang Wang , Ming-Hao Wu
Abstract: The present disclosure provides a printed circuit board and a method thereof. The printed circuit board has a first substrate, at least one first trace layer and at least one second trace layer. The first substrate has a first surface and a second surface. The first surface and the second surface are corresponding to each other along an axis. The first trace layer is formed on the first surface and/or the second surface of the first substrate. The first trace layer has at least one first trace and at least one first gap beside the first trace by etching. The second trace layer is formed on the first trace layer. The second trace layer has at least one second trace and at least one second gap beside the second trace by etching.
-
公开(公告)号:US12225669B2
公开(公告)日:2025-02-11
申请号:US16966766
申请日:2019-10-01
Applicant: LG CHEM, LTD.
Inventor: Hyung Suk Oh , Kwanghee Jung , Chul Young Kim , Ji Hyup Kim
Abstract: The present disclosure relates to a manufacturing method of a continuous sheet for circuit board production providing reel type laminates in a roll-to-roll continuous process without a belt press by connecting at least two or more sheet type metal laminates using an adhesion substrate which includes a reinforcement film and a conductor, the manufacturing method providing improved mechanical properties, and excellent chemical resistance and productivity, and the continuous sheet for circuit board production manufactured therefrom.
-
公开(公告)号:US20250048562A1
公开(公告)日:2025-02-06
申请号:US18789154
申请日:2024-07-30
Applicant: IBIDEN CO., LTD.
Inventor: Masashi KUWABARA , Susumu KAGOHASHI , Jun SAKAI , Kyohei YOSHIKAWA , Takuya INISHI
Abstract: A wiring substrate includes a core substrate including a glass substrate and a through-hole conductor, a resin insulating layer having an opening extending through the resin insulating layer, a conductor layer including a seed layer and an electrolytic plating layer on the seed layer, and a via conductor formed in the opening such that the via conductor electrically connects to the through-hole conductor in the core substrate and includes the seed layer and electrolytic plating layer extending from the conductor layer. The resin insulating layer includes resin and inorganic particles including first and second particles such that the first particles are partially embedded in the resin and that the second particles are embedded in the resin, the first particles have first portions protruding from the resin and second portions embedded in the resin respectively, the surface includes the resin and exposed surfaces of the first portions exposed from the resin.
-
公开(公告)号:US20250048559A1
公开(公告)日:2025-02-06
申请号:US18798062
申请日:2024-08-08
Applicant: LOOMIA Technologies, Inc.
Inventor: Madison Thea MAXEY , Janett MARTINEZ , Ezgi UÇAR
Abstract: A mechanical subtractive method of manufacturing a flexible circuitry layer may include mechanically removing at least a portion of a conductive mesh, wherein, following the mechanical removal, a remaining portion of the conductive mesh forms at least a portion of a circuitry trace comprising an electrode; forming an electrical connection between the electrode and a terminal of an interfacing component, wherein the interfacing component comprises a connector; and encasing at least a portion of the circuit trace with an insulative layer.
-
10.
公开(公告)号:US20250040060A1
公开(公告)日:2025-01-30
申请号:US18269700
申请日:2022-10-21
Inventor: Wangcan Cai , Saifeng Li , Nanjia Zhou
Abstract: The present disclosure relates to a high-precision multilayer PCB and a 3D printing preparation method thereof. The method includes: S1, forming a 3D circuit layer on an upper surface of a substrate; S2, forming a metal pillar at a preset position of the current 3D circuit layer by stacking; S3, forming an insulating layer on an upper surface of the current 3D circuit layer, and leading the corresponding metal pillar out of the formed insulating layer in advance by drilling a hole in the insulating layer and filling the drilled hole with the nanoscale metal slurry; S4, forming a pad layer on an upper surface of the current insulating layer and executing step S5 if the current insulating layer is a top layer; repeatedly executing steps S1 and S2 by using the current insulating layer as a new substrate and executing step S6 if not; S5, connecting the corresponding metal pillar or leading it out in advance and connecting to the pad layer, to complete the preparation of the multilayer PCB; and S6, connecting the corresponding metal pillar or leading it out in advance and connecting to the current 3D circuit layer, and returning to step S3. According to the present disclosure, the high-precision multilayer PCB with high interconnect precision can be prepared.
-
-
-
-
-
-
-
-
-